Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72726560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26836222

1

T1

149

T2

54

T3

100

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88796399	1			T1	111351		T2	90509		T3	5926
values[0x0]	5081913	1			T1	124		T2	40		T3	84
values[0x1]	5684470	1			T1	138		T2	39		T3	94

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49995034	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

49567748

1

T1

37247

T2

45180

T3

2067

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	368984	1			T1	256		T2	1		T3	21
valid_sources[0x01]	377753	1			T1	427		T3	19		T4	3
valid_sources[0x02]	369838	1			T1	323		T3	31		T6	441
valid_sources[0x03]	374467	1			T1	472		T3	24		T6	476
valid_sources[0x04]	380415	1			T1	392		T3	27		T4	3
valid_sources[0x05]	355501	1			T1	508		T3	25		T4	5
valid_sources[0x06]	544071	1			T1	555		T2	325		T3	15
valid_sources[0x07]	411113	1			T1	325		T3	31		T6	442
valid_sources[0x08]	415240	1			T1	411		T3	16		T4	4
valid_sources[0x09]	375870	1			T1	406		T3	27		T4	1
valid_sources[0x0a]	376465	1			T1	829		T3	15		T4	3
valid_sources[0x0b]	367752	1			T1	307		T3	26		T4	4
valid_sources[0x0c]	359372	1			T1	461		T3	24		T4	1
valid_sources[0x0d]	388001	1			T1	343		T3	14		T4	6
valid_sources[0x0e]	381569	1			T1	588		T3	35		T4	1
valid_sources[0x0f]	421392	1			T1	401		T3	28		T4	6
valid_sources[0x10]	370890	1			T1	460		T3	19		T6	484
valid_sources[0x11]	372970	1			T1	347		T3	24		T6	496
valid_sources[0x12]	453101	1			T1	631		T3	30		T4	2
valid_sources[0x13]	418888	1			T1	515		T3	18		T5	22
valid_sources[0x14]	367981	1			T1	356		T3	26		T4	1
valid_sources[0x15]	424387	1			T1	478		T3	24		T4	2
valid_sources[0x16]	368634	1			T1	466		T3	22		T4	2
valid_sources[0x17]	366154	1			T1	257		T2	5367		T3	26
valid_sources[0x18]	386406	1			T1	476		T3	16		T4	2
valid_sources[0x19]	360764	1			T1	765		T3	18		T4	3
valid_sources[0x1a]	370786	1			T1	342		T3	24		T4	2
valid_sources[0x1b]	361034	1			T1	534		T3	31		T5	1
valid_sources[0x1c]	464026	1			T1	580		T3	26		T6	460
valid_sources[0x1d]	370220	1			T1	546		T2	5365		T3	17
valid_sources[0x1e]	404891	1			T1	522		T3	20		T4	3
valid_sources[0x1f]	412474	1			T1	335		T3	21		T5	2
valid_sources[0x20]	359504	1			T1	427		T3	25		T4	2
valid_sources[0x21]	510014	1			T1	355		T3	30		T6	459
valid_sources[0x22]	393745	1			T1	329		T3	25		T6	467
valid_sources[0x23]	361808	1			T1	420		T3	27		T4	4
valid_sources[0x24]	390913	1			T1	342		T3	33		T4	4
valid_sources[0x25]	383910	1			T1	431		T3	23		T4	2
valid_sources[0x26]	417065	1			T1	270		T3	22		T4	2
valid_sources[0x27]	362072	1			T1	341		T3	22		T4	1
valid_sources[0x28]	387257	1			T1	694		T3	15		T4	1
valid_sources[0x29]	383921	1			T1	471		T3	14		T4	6
valid_sources[0x2a]	371689	1			T1	294		T3	22		T4	1
valid_sources[0x2b]	363822	1			T1	566		T3	22		T4	5
valid_sources[0x2c]	392652	1			T1	365		T3	32		T4	1
valid_sources[0x2d]	399718	1			T1	384		T3	23		T4	2
valid_sources[0x2e]	364459	1			T1	388		T3	31		T4	2
valid_sources[0x2f]	474098	1			T1	439		T3	29		T4	1
valid_sources[0x30]	375516	1			T1	294		T2	1		T3	25
valid_sources[0x31]	364672	1			T1	615		T3	15		T4	3
valid_sources[0x32]	351011	1			T1	476		T3	28		T4	6
valid_sources[0x33]	355641	1			T1	482		T3	22		T5	5
valid_sources[0x34]	351154	1			T1	255		T3	13		T4	1
valid_sources[0x35]	369418	1			T1	400		T3	16		T4	2
valid_sources[0x36]	399062	1			T1	452		T3	26		T4	2
valid_sources[0x37]	390672	1			T1	473		T3	20		T5	4
valid_sources[0x38]	466852	1			T1	369		T3	22		T4	4
valid_sources[0x39]	385098	1			T1	630		T3	17		T4	2
valid_sources[0x3a]	395096	1			T1	380		T3	29		T4	1
valid_sources[0x3b]	407964	1			T1	302		T3	20		T4	1
valid_sources[0x3c]	407326	1			T1	293		T3	16		T4	2
valid_sources[0x3d]	389733	1			T1	418		T3	31		T4	2
valid_sources[0x3e]	392784	1			T1	572		T3	25		T4	4
valid_sources[0x3f]	473106	1			T1	487		T3	32		T6	462
valid_sources[0x40]	390901	1			T1	724		T3	29		T6	509
valid_sources[0x41]	513462	1			T1	429		T3	28		T4	3
valid_sources[0x42]	383816	1			T1	322		T3	20		T4	1
valid_sources[0x43]	382375	1			T1	367		T3	21		T4	5
valid_sources[0x44]	366774	1			T1	562		T3	17		T4	2
valid_sources[0x45]	377629	1			T1	446		T3	29		T4	1
valid_sources[0x46]	359047	1			T1	376		T3	15		T4	4
valid_sources[0x47]	393708	1			T1	520		T3	23		T4	7
valid_sources[0x48]	383418	1			T1	508		T2	5289		T3	19
valid_sources[0x49]	382131	1			T1	310		T2	5365		T3	19
valid_sources[0x4a]	391437	1			T1	492		T3	37		T6	484
valid_sources[0x4b]	386144	1			T1	424		T3	31		T4	1
valid_sources[0x4c]	403867	1			T1	536		T3	27		T4	1
valid_sources[0x4d]	411741	1			T1	458		T3	8		T4	3
valid_sources[0x4e]	424862	1			T1	477		T3	29		T4	5
valid_sources[0x4f]	403137	1			T1	424		T3	23		T4	1
valid_sources[0x50]	434124	1			T1	393		T3	23		T4	2
valid_sources[0x51]	516007	1			T1	489		T2	15068		T3	25
valid_sources[0x52]	410805	1			T1	255		T3	35		T4	3
valid_sources[0x53]	361766	1			T1	474		T3	19		T5	3
valid_sources[0x54]	386327	1			T1	467		T2	9664		T3	27
valid_sources[0x55]	362824	1			T1	588		T3	26		T4	2
valid_sources[0x56]	353310	1			T1	439		T3	28		T4	2
valid_sources[0x57]	394445	1			T1	412		T3	24		T5	3
valid_sources[0x58]	379382	1			T1	650		T3	35		T6	501
valid_sources[0x59]	402903	1			T1	609		T3	24		T4	2
valid_sources[0x5a]	373381	1			T1	410		T2	4973		T3	27
valid_sources[0x5b]	393393	1			T1	351		T3	15		T4	3
valid_sources[0x5c]	396603	1			T1	354		T3	21		T4	6
valid_sources[0x5d]	392560	1			T1	447		T3	29		T5	18
valid_sources[0x5e]	360752	1			T1	323		T3	21		T4	4
valid_sources[0x5f]	418686	1			T1	387		T3	10		T4	2
valid_sources[0x60]	347012	1			T1	462		T3	27		T4	4
valid_sources[0x61]	361018	1			T1	363		T2	4653		T3	37
valid_sources[0x62]	360607	1			T1	548		T3	22		T4	1
valid_sources[0x63]	367547	1			T1	518		T3	20		T4	2
valid_sources[0x64]	362342	1			T1	581		T3	23		T4	4
valid_sources[0x65]	369344	1			T1	627		T3	26		T4	10
valid_sources[0x66]	383786	1			T1	309		T3	32		T4	3
valid_sources[0x67]	387773	1			T1	498		T3	12		T4	5
valid_sources[0x68]	408708	1			T1	323		T3	18		T4	4
valid_sources[0x69]	360120	1			T1	337		T3	31		T4	4
valid_sources[0x6a]	469900	1			T1	391		T3	23		T4	3
valid_sources[0x6b]	379624	1			T1	508		T3	25		T4	3
valid_sources[0x6c]	387325	1			T1	498		T3	25		T4	4
valid_sources[0x6d]	368931	1			T1	506		T3	31		T5	12
valid_sources[0x6e]	377236	1			T1	1003		T3	24		T4	3
valid_sources[0x6f]	349898	1			T1	598		T3	22		T6	500
valid_sources[0x70]	375757	1			T1	330		T3	20		T4	2
valid_sources[0x71]	367170	1			T1	298		T2	1		T3	25
valid_sources[0x72]	360615	1			T1	314		T3	36		T4	4
valid_sources[0x73]	364773	1			T1	456		T3	21		T4	1
valid_sources[0x74]	372291	1			T1	384		T3	17		T4	2
valid_sources[0x75]	418005	1			T1	335		T3	22		T4	3
valid_sources[0x76]	395584	1			T1	661		T3	17		T4	3
valid_sources[0x77]	418675	1			T1	387		T3	19		T4	2
valid_sources[0x78]	515520	1			T1	416		T3	18		T6	524
valid_sources[0x79]	391682	1			T1	762		T2	4655		T3	12
valid_sources[0x7a]	375159	1			T1	551		T3	23		T4	1
valid_sources[0x7b]	379070	1			T1	449		T3	37		T4	1
valid_sources[0x7c]	368217	1			T1	283		T3	31		T4	3
valid_sources[0x7d]	364433	1			T1	459		T3	25		T6	495
valid_sources[0x7e]	391171	1			T1	350		T3	22		T4	1
valid_sources[0x7f]	483873	1			T1	487		T3	25		T6	514
valid_sources[0x80]	395472	1			T1	452		T3	20		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17250318

1

T1

73

T2

1

T3

37

values[0x0]

all_enables

biggest_size

4820554

1

T1

47

T2

28

T3

36

values[0x1]

all_enables

biggest_size

4765350

1

T1

29

T2

25

T3

27