Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	16149240	0	0
ctrl_rd_A	2147483647	175606	0	0
intr_enable_rd_A	2147483647	154917	0	0
ovrd_rd_A	2147483647	175475	0	0
timeout_ctrl_rd_A	2147483647	174620	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16149240	0	0
T6	145892	31740	0	0
T7	213299	0	0	0
T8	843291	0	0	0
T9	254912	98905	0	0
T10	51122	0	0	0
T11	361222	0	0	0
T12	203414	0	0	0
T13	379013	138921	0	0
T24	0	160585	0	0
T25	0	191725	0	0
T26	0	97970	0	0
T27	0	128259	0	0
T28	0	181385	0	0
T29	0	59555	0	0
T30	0	120554	0	0
T31	297003	0	0	0
T32	357005	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	175606	0	0
T6	145892	3521	0	0
T7	213299	0	0	0
T8	843291	0	0	0
T9	254912	0	0	0
T10	51122	0	0	0
T11	361222	0	0	0
T12	203414	0	0	0
T13	379013	0	0	0
T26	0	11313	0	0
T28	0	7754	0	0
T31	297003	0	0	0
T32	357005	0	0	0
T46	0	9277	0	0
T105	0	6795	0	0
T106	0	4528	0	0
T107	0	3411	0	0
T108	0	5519	0	0
T109	0	7545	0	0
T110	0	3141	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	154917	0	0
T6	145892	2976	0	0
T7	213299	0	0	0
T8	843291	0	0	0
T9	254912	0	0	0
T10	51122	0	0	0
T11	361222	0	0	0
T12	203414	0	0	0
T13	379013	0	0	0
T14	0	12	0	0
T26	0	10047	0	0
T28	0	6971	0	0
T31	297003	0	0	0
T32	357005	0	0	0
T46	0	7844	0	0
T105	0	6095	0	0
T106	0	4173	0	0
T107	0	3367	0	0
T108	0	5003	0	0
T111	0	17	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	175475	0	0
T6	145892	3422	0	0
T7	213299	0	0	0
T8	843291	0	0	0
T9	254912	0	0	0
T10	51122	0	0	0
T11	361222	0	0	0
T12	203414	0	0	0
T13	379013	0	0	0
T26	0	11091	0	0
T28	0	8020	0	0
T31	297003	0	0	0
T32	357005	0	0	0
T46	0	8843	0	0
T105	0	6954	0	0
T106	0	4395	0	0
T107	0	3705	0	0
T108	0	5644	0	0
T109	0	7793	0	0
T110	0	2938	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	174620	0	0
T6	145892	3172	0	0
T7	213299	0	0	0
T8	843291	0	0	0
T9	254912	0	0	0
T10	51122	0	0	0
T11	361222	0	0	0
T12	203414	0	0	0
T13	379013	0	0	0
T26	0	11006	0	0
T28	0	7954	0	0
T31	297003	0	0	0
T32	357005	0	0	0
T46	0	9762	0	0
T105	0	6919	0	0
T106	0	4636	0	0
T107	0	3475	0	0
T108	0	5787	0	0
T109	0	7951	0	0
T110	0	2720	0	0