Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	78384941	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28412399

1

T1

43170

T2

227

T3

152632

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	96939767	1			T1	226803		T2	1793		T3	68639
values[0x0]	4657003	1			T1	1015		T2	211		T3	57915
values[0x1]	5200570	1			T1	988		T2	248		T3	65809

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54197708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52599632

1

T1

99077

T2

850

T3

168550

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	435656	1			T1	866		T3	266		T6	11
valid_sources[0x01]	396260	1			T1	890		T3	523		T6	20
valid_sources[0x02]	519500	1			T1	1026		T3	959		T6	11
valid_sources[0x03]	402906	1			T1	922		T3	447		T4	5
valid_sources[0x04]	404722	1			T1	965		T3	1019		T6	16
valid_sources[0x05]	441574	1			T1	1026		T3	3463		T6	26
valid_sources[0x06]	391670	1			T1	817		T3	278		T6	16
valid_sources[0x07]	467507	1			T1	677		T3	730		T6	21
valid_sources[0x08]	397601	1			T1	953		T3	656		T6	21
valid_sources[0x09]	400905	1			T1	873		T3	986		T6	32
valid_sources[0x0a]	392463	1			T1	859		T3	1298		T6	22
valid_sources[0x0b]	392827	1			T1	876		T3	480		T6	26
valid_sources[0x0c]	382772	1			T1	981		T3	533		T6	16
valid_sources[0x0d]	422571	1			T1	1004		T3	880		T6	17
valid_sources[0x0e]	389312	1			T1	815		T3	969		T6	25
valid_sources[0x0f]	433187	1			T1	958		T3	622		T4	1
valid_sources[0x10]	502282	1			T1	1055		T3	426		T6	17
valid_sources[0x11]	446841	1			T1	806		T3	771		T6	16
valid_sources[0x12]	399967	1			T1	1005		T3	1013		T6	18
valid_sources[0x13]	422533	1			T1	883		T3	955		T6	19
valid_sources[0x14]	437753	1			T1	897		T3	733		T4	2
valid_sources[0x15]	399926	1			T1	969		T3	1314		T4	12
valid_sources[0x16]	500228	1			T1	857		T3	709		T6	29
valid_sources[0x17]	404984	1			T1	887		T3	1054		T6	17
valid_sources[0x18]	398750	1			T1	845		T3	337		T5	1
valid_sources[0x19]	398897	1			T1	918		T3	160		T6	15
valid_sources[0x1a]	394793	1			T1	863		T3	830		T6	19
valid_sources[0x1b]	385863	1			T1	856		T3	794		T6	18
valid_sources[0x1c]	386692	1			T1	840		T3	487		T6	17
valid_sources[0x1d]	427358	1			T1	904		T3	911		T6	19
valid_sources[0x1e]	408987	1			T1	777		T3	605		T6	26
valid_sources[0x1f]	477601	1			T1	854		T3	799		T6	21
valid_sources[0x20]	395298	1			T1	894		T3	442		T6	18
valid_sources[0x21]	547019	1			T1	775		T3	547		T6	16
valid_sources[0x22]	382774	1			T1	795		T3	591		T6	19
valid_sources[0x23]	384402	1			T1	1025		T3	2261		T6	19
valid_sources[0x24]	417391	1			T1	917		T3	549		T6	19
valid_sources[0x25]	391464	1			T1	967		T3	1994		T6	17
valid_sources[0x26]	381736	1			T1	769		T3	1087		T6	23
valid_sources[0x27]	382867	1			T1	972		T3	382		T4	34
valid_sources[0x28]	399933	1			T1	961		T3	513		T4	9
valid_sources[0x29]	439641	1			T1	866		T3	537		T6	15
valid_sources[0x2a]	397779	1			T1	973		T3	305		T6	14
valid_sources[0x2b]	443483	1			T1	947		T3	673		T6	20
valid_sources[0x2c]	389920	1			T1	832		T3	241		T6	21
valid_sources[0x2d]	440526	1			T1	962		T3	840		T6	13
valid_sources[0x2e]	481925	1			T1	1015		T3	755		T6	15
valid_sources[0x2f]	413009	1			T1	884		T3	1043		T6	18
valid_sources[0x30]	400878	1			T1	829		T3	615		T6	22
valid_sources[0x31]	386775	1			T1	972		T3	903		T6	18
valid_sources[0x32]	420193	1			T1	848		T3	196		T6	18
valid_sources[0x33]	427839	1			T1	822		T3	615		T6	19
valid_sources[0x34]	395119	1			T1	1051		T3	513		T6	18
valid_sources[0x35]	391109	1			T1	821		T3	261		T6	22
valid_sources[0x36]	376133	1			T1	873		T3	941		T6	16
valid_sources[0x37]	409954	1			T1	742		T3	306		T4	6
valid_sources[0x38]	476648	1			T1	836		T3	587		T6	29
valid_sources[0x39]	405822	1			T1	815		T3	401		T4	24
valid_sources[0x3a]	384856	1			T1	1060		T3	1436		T4	14
valid_sources[0x3b]	392373	1			T1	832		T3	469		T6	14
valid_sources[0x3c]	453590	1			T1	853		T3	1616		T6	17
valid_sources[0x3d]	522632	1			T1	775		T3	1355		T6	21
valid_sources[0x3e]	404074	1			T1	946		T3	1286		T6	15
valid_sources[0x3f]	413102	1			T1	1038		T3	534		T6	14
valid_sources[0x40]	380751	1			T1	917		T3	1867		T6	15
valid_sources[0x41]	447831	1			T1	686		T3	942		T6	15
valid_sources[0x42]	460881	1			T1	898		T3	762		T6	22
valid_sources[0x43]	491995	1			T1	822		T3	262		T6	19
valid_sources[0x44]	403280	1			T1	796		T3	570		T6	20
valid_sources[0x45]	586423	1			T1	1012		T3	280		T6	17
valid_sources[0x46]	416292	1			T1	1012		T3	1237		T6	16
valid_sources[0x47]	408721	1			T1	927		T3	811		T6	21
valid_sources[0x48]	502687	1			T1	713		T3	1065		T4	7
valid_sources[0x49]	422638	1			T1	725		T3	741		T6	20
valid_sources[0x4a]	467610	1			T1	883		T3	704		T6	12
valid_sources[0x4b]	434883	1			T1	881		T3	607		T6	20
valid_sources[0x4c]	381156	1			T1	701		T3	575		T6	10
valid_sources[0x4d]	388783	1			T1	966		T3	788		T6	22
valid_sources[0x4e]	459641	1			T1	934		T3	697		T6	24
valid_sources[0x4f]	403732	1			T1	815		T3	384		T6	20
valid_sources[0x50]	399319	1			T1	930		T3	377		T6	14
valid_sources[0x51]	472994	1			T1	892		T3	556		T6	16
valid_sources[0x52]	404333	1			T1	752		T3	599		T6	14
valid_sources[0x53]	423339	1			T1	769		T3	142		T6	20
valid_sources[0x54]	438251	1			T1	941		T3	803		T6	19
valid_sources[0x55]	369987	1			T1	860		T3	527		T6	22
valid_sources[0x56]	444784	1			T1	925		T3	733		T6	18
valid_sources[0x57]	423313	1			T1	896		T3	419		T6	17
valid_sources[0x58]	390673	1			T1	897		T3	944		T6	21
valid_sources[0x59]	434285	1			T1	789		T3	930		T6	27
valid_sources[0x5a]	417378	1			T1	1009		T3	372		T6	20
valid_sources[0x5b]	399268	1			T1	814		T3	909		T6	24
valid_sources[0x5c]	409388	1			T1	1049		T3	903		T6	21
valid_sources[0x5d]	404331	1			T1	837		T3	656		T6	21
valid_sources[0x5e]	393804	1			T1	813		T3	586		T4	13
valid_sources[0x5f]	384372	1			T1	891		T3	501		T6	20
valid_sources[0x60]	406881	1			T1	798		T3	566		T6	21
valid_sources[0x61]	387679	1			T1	892		T3	1042		T6	13
valid_sources[0x62]	463582	1			T1	654		T3	975		T4	3
valid_sources[0x63]	411732	1			T1	977		T3	500		T4	9
valid_sources[0x64]	365389	1			T1	864		T3	341		T6	18
valid_sources[0x65]	390644	1			T1	780		T3	803		T6	20
valid_sources[0x66]	388066	1			T1	1039		T3	482		T6	14
valid_sources[0x67]	397173	1			T1	824		T3	755		T4	9
valid_sources[0x68]	388331	1			T1	805		T3	862		T6	13
valid_sources[0x69]	397950	1			T1	977		T3	862		T6	18
valid_sources[0x6a]	370009	1			T1	742		T3	386		T6	22
valid_sources[0x6b]	396956	1			T1	928		T3	428		T4	20
valid_sources[0x6c]	393284	1			T1	872		T3	625		T4	2
valid_sources[0x6d]	382435	1			T1	924		T3	1077		T6	21
valid_sources[0x6e]	458984	1			T1	943		T3	638		T6	23
valid_sources[0x6f]	406621	1			T1	876		T3	572		T6	19
valid_sources[0x70]	435088	1			T1	767		T3	1686		T6	19
valid_sources[0x71]	386454	1			T1	826		T3	862		T6	14
valid_sources[0x72]	424406	1			T1	805		T3	839		T4	16
valid_sources[0x73]	374627	1			T1	979		T3	1356		T6	13
valid_sources[0x74]	394542	1			T1	881		T3	160		T6	22
valid_sources[0x75]	387404	1			T1	846		T3	504		T6	23
valid_sources[0x76]	470757	1			T1	838		T3	545		T6	23
valid_sources[0x77]	387236	1			T1	778		T3	2174		T6	19
valid_sources[0x78]	382585	1			T1	789		T3	1082		T6	19
valid_sources[0x79]	386603	1			T1	974		T3	533		T4	4
valid_sources[0x7a]	415406	1			T1	775		T3	1054		T6	29
valid_sources[0x7b]	433655	1			T1	940		T3	817		T6	26
valid_sources[0x7c]	635985	1			T1	913		T3	297		T6	20
valid_sources[0x7d]	379145	1			T1	800		T3	1155		T6	13
valid_sources[0x7e]	402813	1			T1	981		T3	803		T6	15
valid_sources[0x7f]	400166	1			T1	740		T3	764		T6	22
valid_sources[0x80]	381332	1			T1	1152		T3	418		T6	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19702880

1

T1

42667

T2

97

T3

38401

values[0x0]

all_enables

biggest_size

4385242

1

T1

323

T2

75

T3

57099

values[0x1]

all_enables

biggest_size

4324277

1

T1

180

T2

55

T3

57132