Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14555357	0	0
ctrl_rd_A	2147483647	167164	0	0
intr_enable_rd_A	2147483647	148836	0	0
ovrd_rd_A	2147483647	165877	0	0
timeout_ctrl_rd_A	2147483647	166332	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14555357	0	0
T3	493294	201224	0	0
T4	129631	0	0	0
T5	328732	0	0	0
T6	268056	0	0	0
T7	442655	0	0	0
T8	487657	0	0	0
T9	141848	0	0	0
T10	199029	0	0	0
T11	119751	0	0	0
T12	446960	0	0	0
T14	0	112759	0	0
T21	0	117063	0	0
T29	0	175850	0	0
T30	0	260761	0	0
T31	0	119505	0	0
T32	0	95633	0	0
T33	0	216417	0	0
T34	0	108105	0	0
T35	0	111289	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	167164	0	0
T14	442315	12615	0	0
T15	186434	0	0	0
T16	994864	0	0	0
T20	444393	0	0	0
T23	712	0	0	0
T35	0	12674	0	0
T119	0	7679	0	0
T120	0	9293	0	0
T121	0	1777	0	0
T122	0	8811	0	0
T123	0	2508	0	0
T124	0	7306	0	0
T125	0	1647	0	0
T126	0	19360	0	0
T127	24618	0	0	0
T128	125294	0	0	0
T129	165625	0	0	0
T130	230885	0	0	0
T131	120812	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	148836	0	0
T14	442315	11571	0	0
T15	186434	0	0	0
T16	994864	0	0	0
T20	444393	0	0	0
T23	712	0	0	0
T35	0	11051	0	0
T119	0	7032	0	0
T120	0	8118	0	0
T121	0	1553	0	0
T122	0	7677	0	0
T123	0	2192	0	0
T124	0	6247	0	0
T127	24618	0	0	0
T128	125294	0	0	0
T129	165625	0	0	0
T130	230885	0	0	0
T131	120812	0	0	0
T132	0	22	0	0
T133	0	16	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	165877	0	0
T14	442315	12513	0	0
T15	186434	0	0	0
T16	994864	0	0	0
T20	444393	0	0	0
T23	712	0	0	0
T35	0	13299	0	0
T119	0	7795	0	0
T120	0	9528	0	0
T121	0	1710	0	0
T122	0	9009	0	0
T123	0	2583	0	0
T124	0	7118	0	0
T125	0	1715	0	0
T126	0	19847	0	0
T127	24618	0	0	0
T128	125294	0	0	0
T129	165625	0	0	0
T130	230885	0	0	0
T131	120812	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	166332	0	0
T14	442315	12684	0	0
T15	186434	0	0	0
T16	994864	0	0	0
T20	444393	0	0	0
T23	712	0	0	0
T35	0	12730	0	0
T119	0	7881	0	0
T120	0	9378	0	0
T121	0	1866	0	0
T122	0	9362	0	0
T123	0	2907	0	0
T124	0	7109	0	0
T125	0	1660	0	0
T126	0	19555	0	0
T127	24618	0	0	0
T128	125294	0	0	0
T129	165625	0	0	0
T130	230885	0	0	0
T131	120812	0	0	0