Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74218765	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27771164

1

T1

55

T2

2

T3

557

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	91943479	1			T1	168		T2	1		T3	2390
values[0x0]	4746125	1			T1	16		T2	1		T3	197
values[0x1]	5300325	1			T1	14		T2	2		T3	228

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51250725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50739204

1

T1

94

T2

3

T3

1187

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	380400	1			T3	10		T4	1		T5	106
valid_sources[0x01]	469927	1			T1	2		T3	12		T4	1
valid_sources[0x02]	389414	1			T3	14		T5	76		T6	33
valid_sources[0x03]	376220	1			T3	14		T5	90		T6	27
valid_sources[0x04]	368897	1			T3	8		T4	2		T5	85
valid_sources[0x05]	399579	1			T3	8		T5	89		T6	42
valid_sources[0x06]	385393	1			T1	2		T3	18		T4	2
valid_sources[0x07]	368838	1			T3	12		T4	1		T5	79
valid_sources[0x08]	389358	1			T3	6		T4	4		T5	82
valid_sources[0x09]	398025	1			T1	1		T3	4		T5	85
valid_sources[0x0a]	347837	1			T1	2		T3	12		T5	67
valid_sources[0x0b]	390597	1			T1	2		T3	9		T4	3
valid_sources[0x0c]	363398	1			T3	7		T5	74		T6	58
valid_sources[0x0d]	430076	1			T1	1		T3	13		T5	100
valid_sources[0x0e]	479842	1			T1	1		T3	10		T4	3
valid_sources[0x0f]	366166	1			T3	13		T5	93		T6	73
valid_sources[0x10]	391538	1			T1	1		T3	14		T4	5
valid_sources[0x11]	415815	1			T3	14		T4	7		T5	65
valid_sources[0x12]	431686	1			T3	12		T4	9		T5	73
valid_sources[0x13]	357112	1			T1	1		T3	14		T5	93
valid_sources[0x14]	379023	1			T1	2		T3	5		T5	104
valid_sources[0x15]	415858	1			T3	5		T5	75		T6	16
valid_sources[0x16]	353606	1			T1	1		T3	9		T5	95
valid_sources[0x17]	418103	1			T1	2		T3	8		T4	1
valid_sources[0x18]	383353	1			T3	10		T4	2		T5	89
valid_sources[0x19]	343574	1			T1	1		T3	17		T5	103
valid_sources[0x1a]	570395	1			T1	1		T3	17		T5	105
valid_sources[0x1b]	348010	1			T1	5		T3	15		T4	4
valid_sources[0x1c]	415868	1			T1	3		T3	6		T4	4
valid_sources[0x1d]	371963	1			T1	2		T3	8		T4	15
valid_sources[0x1e]	392700	1			T3	20		T5	104		T6	48
valid_sources[0x1f]	365462	1			T3	9		T4	3		T5	81
valid_sources[0x20]	432724	1			T3	12		T5	87		T6	52
valid_sources[0x21]	448593	1			T3	16		T5	74		T6	16
valid_sources[0x22]	427224	1			T3	21		T5	73		T6	26
valid_sources[0x23]	398894	1			T1	6		T3	6		T5	74
valid_sources[0x24]	415637	1			T3	16		T4	3		T5	101
valid_sources[0x25]	401553	1			T1	2		T3	8		T4	3
valid_sources[0x26]	437090	1			T1	2		T3	11		T5	99
valid_sources[0x27]	375012	1			T3	14		T5	73		T6	46
valid_sources[0x28]	388365	1			T1	1		T3	11		T5	55
valid_sources[0x29]	417751	1			T1	1		T3	11		T5	60
valid_sources[0x2a]	373419	1			T3	19		T5	89		T6	34
valid_sources[0x2b]	377891	1			T1	1		T3	11		T4	1
valid_sources[0x2c]	360671	1			T1	2		T3	5		T4	8
valid_sources[0x2d]	472742	1			T1	2		T3	13		T5	81
valid_sources[0x2e]	346897	1			T3	11		T5	69		T6	23
valid_sources[0x2f]	372445	1			T1	1		T3	12		T5	77
valid_sources[0x30]	543823	1			T1	1		T3	11		T5	95
valid_sources[0x31]	363423	1			T1	2		T3	5		T5	70
valid_sources[0x32]	379341	1			T1	1		T3	14		T5	78
valid_sources[0x33]	379031	1			T3	13		T5	94		T6	53
valid_sources[0x34]	452191	1			T1	2		T3	10		T5	74
valid_sources[0x35]	382967	1			T1	3		T3	14		T4	8
valid_sources[0x36]	371115	1			T1	2		T3	4		T4	18
valid_sources[0x37]	365980	1			T1	1		T3	7		T4	4
valid_sources[0x38]	396211	1			T1	1		T3	9		T4	2
valid_sources[0x39]	394809	1			T1	2		T3	10		T4	6
valid_sources[0x3a]	419037	1			T1	2		T3	3		T4	1
valid_sources[0x3b]	381312	1			T1	3		T3	17		T4	2
valid_sources[0x3c]	510996	1			T1	1		T3	4		T5	49
valid_sources[0x3d]	543941	1			T3	12		T5	74		T6	23
valid_sources[0x3e]	349818	1			T1	1		T3	10		T5	74
valid_sources[0x3f]	355612	1			T1	1		T3	11		T5	61
valid_sources[0x40]	372105	1			T3	11		T5	83		T6	45
valid_sources[0x41]	379224	1			T3	10		T4	3		T5	76
valid_sources[0x42]	353945	1			T1	2		T3	17		T4	2
valid_sources[0x43]	372713	1			T1	1		T3	12		T4	4
valid_sources[0x44]	438864	1			T3	8		T4	19		T5	92
valid_sources[0x45]	359855	1			T1	3		T3	10		T5	87
valid_sources[0x46]	341910	1			T1	1		T3	8		T4	4
valid_sources[0x47]	392094	1			T3	13		T4	19		T5	81
valid_sources[0x48]	381743	1			T1	1		T3	10		T5	93
valid_sources[0x49]	377892	1			T3	8		T5	93		T6	34
valid_sources[0x4a]	349330	1			T1	5		T3	13		T5	74
valid_sources[0x4b]	359310	1			T3	9		T4	4		T5	68
valid_sources[0x4c]	395474	1			T3	11		T5	101		T6	44
valid_sources[0x4d]	377277	1			T3	14		T4	5		T5	90
valid_sources[0x4e]	395057	1			T3	5		T4	2		T5	87
valid_sources[0x4f]	428054	1			T1	1		T3	11		T4	1
valid_sources[0x50]	549592	1			T3	8		T4	5		T5	77
valid_sources[0x51]	440704	1			T3	8		T4	7		T5	84
valid_sources[0x52]	385300	1			T3	20		T4	6		T5	70
valid_sources[0x53]	427800	1			T3	9		T4	4		T5	78
valid_sources[0x54]	379783	1			T3	12		T5	63		T6	35
valid_sources[0x55]	409027	1			T3	6		T4	1		T5	91
valid_sources[0x56]	365094	1			T1	1		T3	16		T4	12
valid_sources[0x57]	421610	1			T1	1		T3	6		T5	93
valid_sources[0x58]	387484	1			T3	10		T4	4		T5	92
valid_sources[0x59]	368420	1			T1	4		T3	15		T4	4
valid_sources[0x5a]	389992	1			T3	9		T4	7		T5	88
valid_sources[0x5b]	371594	1			T3	15		T4	7		T5	78
valid_sources[0x5c]	369997	1			T3	7		T4	4		T5	118
valid_sources[0x5d]	366525	1			T3	19		T5	79		T6	41
valid_sources[0x5e]	345931	1			T3	10		T5	77		T6	38
valid_sources[0x5f]	352454	1			T1	3		T3	8		T4	3
valid_sources[0x60]	412343	1			T1	1		T3	19		T5	104
valid_sources[0x61]	363461	1			T3	15		T4	7		T5	76
valid_sources[0x62]	666008	1			T3	18		T5	76		T6	49
valid_sources[0x63]	377210	1			T3	4		T5	86		T6	31
valid_sources[0x64]	379925	1			T3	10		T4	18		T5	54
valid_sources[0x65]	369801	1			T3	11		T5	81		T6	25
valid_sources[0x66]	372808	1			T1	1		T3	10		T5	78
valid_sources[0x67]	359576	1			T1	3		T3	12		T4	1
valid_sources[0x68]	452375	1			T3	15		T5	82		T6	45
valid_sources[0x69]	377747	1			T3	12		T5	102		T6	47
valid_sources[0x6a]	374344	1			T1	2		T3	17		T5	104
valid_sources[0x6b]	398694	1			T1	1		T3	15		T4	1
valid_sources[0x6c]	374990	1			T1	3		T3	12		T5	93
valid_sources[0x6d]	396519	1			T3	13		T4	9		T5	78
valid_sources[0x6e]	378541	1			T1	1		T3	16		T4	7
valid_sources[0x6f]	378838	1			T1	1		T3	18		T4	1
valid_sources[0x70]	390792	1			T3	17		T5	85		T6	42
valid_sources[0x71]	357856	1			T3	18		T5	82		T6	48
valid_sources[0x72]	431845	1			T3	9		T5	68		T6	71
valid_sources[0x73]	411310	1			T3	14		T5	89		T6	25
valid_sources[0x74]	488703	1			T3	13		T5	65		T6	29
valid_sources[0x75]	392431	1			T3	9		T5	74		T6	37
valid_sources[0x76]	372553	1			T1	2		T3	10		T5	100
valid_sources[0x77]	350006	1			T3	14		T4	2		T5	86
valid_sources[0x78]	351336	1			T3	10		T5	102		T6	68
valid_sources[0x79]	368294	1			T1	1		T3	11		T4	4
valid_sources[0x7a]	371494	1			T1	2		T3	3		T4	2
valid_sources[0x7b]	413399	1			T3	17		T4	2		T5	79
valid_sources[0x7c]	423225	1			T3	9		T4	3		T5	81
valid_sources[0x7d]	394303	1			T1	2		T3	14		T5	70
valid_sources[0x7e]	415708	1			T1	1		T3	23		T4	5
valid_sources[0x7f]	384699	1			T3	12		T5	85		T6	47
valid_sources[0x80]	358349	1			T3	10		T4	3		T5	110

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18856117

1

T1

47

T2

1

T3

427

values[0x0]

all_enables

biggest_size

4483451

1

T1

7

T2

1

T3

75

values[0x1]

all_enables

biggest_size

4431596

1

T1

1

T3

55

T4

34