Unified Coverage Report :: Module :: uart_reg_top

Module : uart_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.28	99.04	98.85	100.00		98.50	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_llpbk	100.00	100.00	100.00			100.00
u_ctrl_nco	100.00	100.00	100.00			100.00
u_ctrl_nf	100.00	100.00	100.00			100.00
u_ctrl_parity_en	100.00	100.00	100.00			100.00
u_ctrl_parity_odd	100.00	100.00	100.00			100.00
u_ctrl_rx	100.00	100.00	100.00			100.00
u_ctrl_rxblvl	100.00	100.00	100.00			100.00
u_ctrl_slpbk	100.00	100.00	100.00			100.00
u_ctrl_tx	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_rxilvl	96.30	100.00	88.89			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txilvl	96.30	100.00	88.89			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_fifo_status_rxlvl	100.00	100.00
u_fifo_status_txlvl	100.00	100.00
u_intr_enable_rx_break_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_frame_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_parity_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_timeout	100.00	100.00	100.00			100.00
u_intr_enable_rx_watermark	100.00	100.00	100.00			100.00
u_intr_enable_tx_empty	100.00	100.00	100.00			100.00
u_intr_enable_tx_watermark	100.00	100.00	100.00			100.00
u_intr_state_rx_break_err	100.00	100.00	100.00			100.00
u_intr_state_rx_frame_err	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_parity_err	100.00	100.00	100.00			100.00
u_intr_state_rx_timeout	100.00	100.00	100.00			100.00
u_intr_state_rx_watermark	62.59	77.78	50.00			60.00
u_intr_state_tx_empty	100.00	100.00	100.00			100.00
u_intr_state_tx_watermark	62.59	77.78	50.00			60.00
u_intr_test_rx_break_err	100.00	100.00
u_intr_test_rx_frame_err	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_parity_err	100.00	100.00
u_intr_test_rx_timeout	100.00	100.00
u_intr_test_rx_watermark	100.00	100.00
u_intr_test_tx_empty	100.00	100.00
u_intr_test_tx_watermark	100.00	100.00
u_ovrd_txen	100.00	100.00	100.00			100.00
u_ovrd_txval	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_rdata	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_rxidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_status_txidle	100.00	100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_val	100.00	100.00
u_wdata	100.00	100.00	100.00			100.00
u_wdata0_qe	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : uart_reg_top

	Line No.	Total	Covered	Percent
TOTAL		166	166	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	660	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	755	1	1	100.00
CONT_ASSIGN	771	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	793	1	1	100.00
CONT_ASSIGN	807	1	1	100.00
CONT_ASSIGN	1200	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
ALWAYS	1491	14	14	100.00
CONT_ASSIGN	1507	1	1	100.00
ALWAYS	1511	1	1	100.00
CONT_ASSIGN	1528	1	1	100.00
CONT_ASSIGN	1530	1	1	100.00
CONT_ASSIGN	1532	1	1	100.00
CONT_ASSIGN	1534	1	1	100.00
CONT_ASSIGN	1536	1	1	100.00
CONT_ASSIGN	1538	1	1	100.00
CONT_ASSIGN	1540	1	1	100.00
CONT_ASSIGN	1541	1	1	100.00
CONT_ASSIGN	1543	1	1	100.00
CONT_ASSIGN	1545	1	1	100.00
CONT_ASSIGN	1547	1	1	100.00
CONT_ASSIGN	1549	1	1	100.00
CONT_ASSIGN	1551	1	1	100.00
CONT_ASSIGN	1553	1	1	100.00
CONT_ASSIGN	1555	1	1	100.00
CONT_ASSIGN	1557	1	1	100.00
CONT_ASSIGN	1558	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1562	1	1	100.00
CONT_ASSIGN	1564	1	1	100.00
CONT_ASSIGN	1566	1	1	100.00
CONT_ASSIGN	1568	1	1	100.00
CONT_ASSIGN	1570	1	1	100.00
CONT_ASSIGN	1572	1	1	100.00
CONT_ASSIGN	1574	1	1	100.00
CONT_ASSIGN	1575	1	1	100.00
CONT_ASSIGN	1577	1	1	100.00
CONT_ASSIGN	1578	1	1	100.00
CONT_ASSIGN	1580	1	1	100.00
CONT_ASSIGN	1582	1	1	100.00
CONT_ASSIGN	1584	1	1	100.00
CONT_ASSIGN	1586	1	1	100.00
CONT_ASSIGN	1588	1	1	100.00
CONT_ASSIGN	1590	1	1	100.00
CONT_ASSIGN	1592	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1596	1	1	100.00
CONT_ASSIGN	1597	1	1	100.00
CONT_ASSIGN	1598	1	1	100.00
CONT_ASSIGN	1599	1	1	100.00
CONT_ASSIGN	1601	1	1	100.00
CONT_ASSIGN	1602	1	1	100.00
CONT_ASSIGN	1604	1	1	100.00
CONT_ASSIGN	1606	1	1	100.00
CONT_ASSIGN	1608	1	1	100.00
CONT_ASSIGN	1610	1	1	100.00
CONT_ASSIGN	1611	1	1	100.00
CONT_ASSIGN	1612	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1616	1	1	100.00
CONT_ASSIGN	1617	1	1	100.00
CONT_ASSIGN	1618	1	1	100.00
CONT_ASSIGN	1620	1	1	100.00
CONT_ASSIGN	1622	1	1	100.00
ALWAYS	1626	14	14	100.00
ALWAYS	1644	55	55	100.00
CONT_ASSIGN	1749	0	0
CONT_ASSIGN	1757	1	1	100.00
CONT_ASSIGN	1758	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
660	1	1
675	1	1
691	1	1
707	1	1
723	1	1
739	1	1
755	1	1
771	1	1
787	1	1
793	1	1
807	1	1
1200	1	1
1241	1	1
1269	1	1
1297	1	1
1325	1	1
1491	1	1
1492	1	1
1493	1	1
1494	1	1
1495	1	1
1496	1	1
1497	1	1
1498	1	1
1499	1	1
1500	1	1
1501	1	1
1502	1	1
1503	1	1
1504	1	1
1507	1	1
1511	1	1
1528	1	1
1530	1	1
1532	1	1
1534	1	1
1536	1	1
1538	1	1
1540	1	1
1541	1	1
1543	1	1
1545	1	1
1547	1	1
1549	1	1
1551	1	1
1553	1	1
1555	1	1
1557	1	1
1558	1	1
1560	1	1
1562	1	1
1564	1	1
1566	1	1
1568	1	1
1570	1	1
1572	1	1
1574	1	1
1575	1	1
1577	1	1
1578	1	1
1580	1	1
1582	1	1
1584	1	1
1586	1	1
1588	1	1
1590	1	1
1592	1	1
1594	1	1
1596	1	1
1597	1	1
1598	1	1
1599	1	1
1601	1	1
1602	1	1
1604	1	1
1606	1	1
1608	1	1
1610	1	1
1611	1	1
1612	1	1
1614	1	1
1616	1	1
1617	1	1
1618	1	1
1620	1	1
1622	1	1
1626	1	1
1627	1	1
1628	1	1
1629	1	1
1630	1	1
1631	1	1
1632	1	1
1633	1	1
1634	1	1
1635	1	1
1636	1	1
1637	1	1
1638	1	1
1639	1	1
1644	1	1
1645	1	1
1647	1	1
1648	1	1
1649	1	1
1650	1	1
1651	1	1
1652	1	1
1653	1	1
1654	1	1
1658	1	1
1659	1	1
1660	1	1
1661	1	1
1662	1	1
1663	1	1
1664	1	1
1665	1	1
1669	1	1
1670	1	1
1671	1	1
1672	1	1
1673	1	1
1674	1	1
1675	1	1
1676	1	1
1680	1	1
1684	1	1
1685	1	1
1686	1	1
1687	1	1
1688	1	1
1689	1	1
1690	1	1
1691	1	1
1692	1	1
1696	1	1
1697	1	1
1698	1	1
1699	1	1
1700	1	1
1701	1	1
1705	1	1
1709	1	1
1713	1	1
1714	1	1
1715	1	1
1716	1	1
1720	1	1
1721	1	1
1725	1	1
1726	1	1
1730	1	1
1734	1	1
1735	1	1
1749		unreachable
1757	1	1
1758	1	1

---

Cond Coverage for Module : uart_reg_top

	Total	Covered	Percent
Conditions	153	153	100.00
Logical	153	153	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T15,T17
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T28,T29
1	0	Covered	T104,T105,T106

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T27,T28,T29
0	1	0	Covered	T104,T105,T106
1	0	0	Covered	T27,T28,T29

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T104,T105,T106
0	1	0	Covered	T12,T15,T17
1	0	0	Covered	T12,T15,T17

 LINE       1492
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1493
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1494
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       1495
 EXPRESSION (reg_addr == uart_reg_pkg::UART_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       1496
 EXPRESSION (reg_addr == uart_reg_pkg::UART_CTRL_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1497
 EXPRESSION (reg_addr == uart_reg_pkg::UART_STATUS_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1498
 EXPRESSION (reg_addr == uart_reg_pkg::UART_RDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1499
 EXPRESSION (reg_addr == uart_reg_pkg::UART_WDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       1500
 EXPRESSION (reg_addr == uart_reg_pkg::UART_FIFO_CTRL_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1501
 EXPRESSION (reg_addr == uart_reg_pkg::UART_FIFO_STATUS_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       1502
 EXPRESSION (reg_addr == uart_reg_pkg::UART_OVRD_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       1503
 EXPRESSION (reg_addr == uart_reg_pkg::UART_VAL_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       1504
 EXPRESSION (reg_addr == uart_reg_pkg::UART_TIMEOUT_CTRL_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1507
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1507
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       1511
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T15,T17

 LINE       1511
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T5,T6,T7
0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T5,T6,T7
0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T5,T6,T7
0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T3,T4,T5
0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T5,T6,T7
0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T5,T6,T7
0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T1,T3,T4
0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T5,T6,T7
0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T5,T6,T7
0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T5,T6,T7
0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T5,T6,T7
0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T5,T6,T7
1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T3,T4

 LINE       1511
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1511
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T5,T6,T7

 LINE       1511
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       1511
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T5,T6
1	1	Covered	T5,T6,T7

 LINE       1511
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T5,T6,T7

 LINE       1511
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T5,T6,T7

 LINE       1511
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       1511
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T6,T7

 LINE       1511
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T5,T6,T7

 LINE       1511
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       1511
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       1511
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       1511
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T5,T6,T7

 LINE       1528
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T15,T17
1	1	1	Covered	T1,T3,T4

 LINE       1541
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T12,T15,T17
1	1	1	Covered	T1,T3,T4

 LINE       1558
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T12,T15,T17
1	1	1	Covered	T12,T17,T102

 LINE       1575
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T12,T15,T17
1	1	1	Covered	T2,T13,T26

 LINE       1578
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T12,T15,T17
1	1	1	Covered	T1,T3,T4

 LINE       1597
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T107,T108,T109
1	1	1	Covered	T1,T3,T4

 LINE       1598
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T104,T105,T106
1	1	1	Covered	T1,T3,T4

 LINE       1599
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T12,T15,T17
1	1	1	Covered	T3,T4,T5

 LINE       1602
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T12,T15,T17
1	1	1	Covered	T1,T3,T4

 LINE       1611
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T105,T110,T107
1	1	1	Covered	T3,T4,T5

 LINE       1612
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T12,T15,T17
1	1	1	Covered	T12,T19,T20

 LINE       1617
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T104,T105,T106
1	1	1	Covered	T12,T16,T15

 LINE       1618
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T12,T15,T17
1	1	1	Covered	T1,T3,T4

---

Branch Coverage for Module : uart_reg_top

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	1507	2	2	100.00
IF	68	3	3	100.00
CASE	1645	14	14	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1507	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T27,T28,T29
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1645	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : uart_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	90306061	0	0
reAfterRv	2147483647	90306061	0	0
rePulse	2147483647	89040335	0	0
wePulse	2147483647	1265726	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90306061	0	0
T1	668520	198	0	0
T2	985	4	0	0
T3	185792	2815	0	0
T4	489480	623	0	0
T5	596491	21115	0	0
T6	150341	10059	0	0
T7	646323	312766	0	0
T8	425725	282	0	0
T9	515849	108228	0	0
T10	34313	1381	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90306061	0	0
T1	668520	198	0	0
T2	985	4	0	0
T3	185792	2815	0	0
T4	489480	623	0	0
T5	596491	21115	0	0
T6	150341	10059	0	0
T7	646323	312766	0	0
T8	425725	282	0	0
T9	515849	108228	0	0
T10	34313	1381	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	89040335	0	0
T1	668520	168	0	0
T2	985	1	0	0
T3	185792	2390	0	0
T4	489480	382	0	0
T5	596491	20922	0	0
T6	150341	9841	0	0
T7	646323	312042	0	0
T8	425725	160	0	0
T9	515849	107938	0	0
T10	34313	1368	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1265726	0	0
T1	668520	30	0	0
T2	985	3	0	0
T3	185792	425	0	0
T4	489480	241	0	0
T5	596491	193	0	0
T6	150341	218	0	0
T7	646323	724	0	0
T8	425725	122	0	0
T9	515849	290	0	0
T10	34313	13	0	0