Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14695387	0	0
ctrl_rd_A	2147483647	292205	0	0
intr_enable_rd_A	2147483647	259254	0	0
ovrd_rd_A	2147483647	290253	0	0
timeout_ctrl_rd_A	2147483647	290984	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14695387	0	0
T12	125963	46553	0	0
T15	0	241944	0	0
T16	468598	0	0	0
T17	0	198624	0	0
T19	51164	0	0	0
T20	0	89764	0	0
T23	86524	0	0	0
T24	0	211346	0	0
T25	0	68359	0	0
T30	0	49098	0	0
T31	0	160008	0	0
T32	0	111650	0	0
T33	0	59085	0	0
T34	977986	0	0	0
T35	327300	0	0	0
T36	308182	0	0	0
T37	383585	0	0	0
T38	825313	0	0	0
T39	429869	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	292205	0	0
T24	928670	23968	0	0
T25	0	3601	0	0
T49	0	13462	0	0
T120	0	9378	0	0
T122	0	3992	0	0
T123	0	10438	0	0
T124	0	11693	0	0
T125	0	6878	0	0
T126	0	1662	0	0
T127	0	3987	0	0
T128	216438	0	0	0
T129	354541	0	0	0
T130	405562	0	0	0
T131	973684	0	0	0
T132	206093	0	0	0
T133	932968	0	0	0
T134	173284	0	0	0
T135	744515	0	0	0
T136	1118	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	259254	0	0
T24	928670	20484	0	0
T25	0	3089	0	0
T49	0	12134	0	0
T102	0	10	0	0
T122	0	3669	0	0
T123	0	9847	0	0
T124	0	10042	0	0
T125	0	5735	0	0
T126	0	1479	0	0
T128	216438	0	0	0
T129	354541	0	0	0
T130	405562	0	0	0
T131	973684	0	0	0
T132	206093	0	0	0
T133	932968	0	0	0
T134	173284	0	0	0
T135	744515	0	0	0
T136	1118	0	0	0
T137	0	26	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	290253	0	0
T24	928670	22492	0	0
T25	0	4036	0	0
T49	0	13868	0	0
T120	0	9646	0	0
T122	0	4186	0	0
T123	0	10827	0	0
T124	0	11356	0	0
T125	0	7191	0	0
T126	0	1838	0	0
T127	0	3969	0	0
T128	216438	0	0	0
T129	354541	0	0	0
T130	405562	0	0	0
T131	973684	0	0	0
T132	206093	0	0	0
T133	932968	0	0	0
T134	173284	0	0	0
T135	744515	0	0	0
T136	1118	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	290984	0	0
T24	928670	22601	0	0
T25	0	3524	0	0
T49	0	13125	0	0
T120	0	9565	0	0
T122	0	4110	0	0
T123	0	10836	0	0
T124	0	11270	0	0
T125	0	6897	0	0
T126	0	1616	0	0
T127	0	4085	0	0
T128	216438	0	0	0
T129	354541	0	0	0
T130	405562	0	0	0
T131	973684	0	0	0
T132	206093	0	0	0
T133	932968	0	0	0
T134	173284	0	0	0
T135	744515	0	0	0
T136	1118	0	0	0