Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	78804185	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27824905

1

T1

102

T2

6

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	96195844	1			T1	79		T2	2751		T3	2445
values[0x0]	4929539	1			T1	77		T2	5		T3	8
values[0x1]	5503707	1			T1	73		T2	6		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54321204	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52307886

1

T1

120

T2

1375

T3

1261

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	429485	1			T4	40		T6	3640		T8	32
valid_sources[0x01]	463285	1			T1	1		T6	3492		T8	49
valid_sources[0x02]	394435	1			T6	3121		T8	65		T11	73
valid_sources[0x03]	411921	1			T6	4137		T8	42		T9	1
valid_sources[0x04]	393324	1			T6	3884		T8	49		T11	61
valid_sources[0x05]	477104	1			T1	3		T6	3589		T8	26
valid_sources[0x06]	397839	1			T6	3423		T8	30		T11	61
valid_sources[0x07]	415876	1			T1	2		T6	3530		T8	54
valid_sources[0x08]	432608	1			T1	1		T6	3471		T8	43
valid_sources[0x09]	448402	1			T6	3484		T8	32		T9	3
valid_sources[0x0a]	445874	1			T1	3		T6	3756		T8	59
valid_sources[0x0b]	394704	1			T1	1		T6	3616		T8	41
valid_sources[0x0c]	579221	1			T6	4093		T8	45		T11	54
valid_sources[0x0d]	429279	1			T3	1		T6	2818		T8	59
valid_sources[0x0e]	387079	1			T6	3441		T8	60		T9	1
valid_sources[0x0f]	422028	1			T1	1		T6	3486		T8	33
valid_sources[0x10]	389308	1			T1	1		T6	4481		T8	34
valid_sources[0x11]	394774	1			T4	7		T6	2799		T8	53
valid_sources[0x12]	389626	1			T1	4		T6	2971		T8	39
valid_sources[0x13]	413896	1			T1	1		T6	3534		T8	27
valid_sources[0x14]	397954	1			T1	1		T6	3555		T8	30
valid_sources[0x15]	385720	1			T1	1		T6	3023		T8	25
valid_sources[0x16]	398333	1			T6	3230		T8	59		T9	1
valid_sources[0x17]	387148	1			T1	2		T6	3359		T8	48
valid_sources[0x18]	427840	1			T6	3457		T8	62		T9	2
valid_sources[0x19]	377966	1			T6	3200		T8	41		T11	60
valid_sources[0x1a]	401693	1			T1	2		T4	14		T6	3810
valid_sources[0x1b]	427602	1			T6	3120		T8	32		T9	2
valid_sources[0x1c]	432091	1			T1	1		T6	3574		T8	29
valid_sources[0x1d]	415551	1			T1	1		T6	3169		T8	44
valid_sources[0x1e]	397131	1			T4	3		T6	3469		T8	27
valid_sources[0x1f]	407054	1			T1	2		T6	3736		T8	57
valid_sources[0x20]	417979	1			T4	13		T6	3784		T8	52
valid_sources[0x21]	390859	1			T1	2		T4	6		T6	2847
valid_sources[0x22]	702444	1			T4	1		T6	3240		T8	40
valid_sources[0x23]	420787	1			T1	1		T6	3514		T7	15673
valid_sources[0x24]	387293	1			T6	3596		T8	33		T9	2
valid_sources[0x25]	412229	1			T1	2		T6	3124		T8	36
valid_sources[0x26]	421605	1			T6	3628		T8	34		T9	1
valid_sources[0x27]	426993	1			T1	5		T6	3294		T8	58
valid_sources[0x28]	386236	1			T6	3792		T8	52		T11	56
valid_sources[0x29]	417891	1			T6	3859		T8	44		T9	2
valid_sources[0x2a]	411469	1			T6	3784		T8	21		T11	60
valid_sources[0x2b]	390698	1			T4	3		T6	3236		T8	38
valid_sources[0x2c]	394052	1			T6	2799		T8	40		T11	35
valid_sources[0x2d]	425606	1			T1	1		T6	3904		T8	32
valid_sources[0x2e]	387471	1			T6	3370		T7	2		T8	39
valid_sources[0x2f]	464011	1			T1	4		T6	3637		T8	51
valid_sources[0x30]	403076	1			T1	1		T6	3280		T8	34
valid_sources[0x31]	415750	1			T1	1		T6	3534		T7	5694
valid_sources[0x32]	392358	1			T6	4356		T8	45		T11	46
valid_sources[0x33]	430695	1			T1	2		T6	3459		T8	48
valid_sources[0x34]	384417	1			T1	2		T6	3156		T8	37
valid_sources[0x35]	430593	1			T4	18		T6	3614		T8	43
valid_sources[0x36]	418322	1			T1	2		T6	3700		T8	29
valid_sources[0x37]	405587	1			T4	1		T6	3412		T8	48
valid_sources[0x38]	387831	1			T1	1		T4	12		T6	3415
valid_sources[0x39]	390472	1			T1	3		T6	3858		T8	23
valid_sources[0x3a]	418879	1			T6	3564		T8	33		T11	53
valid_sources[0x3b]	429874	1			T1	2		T6	3500		T8	58
valid_sources[0x3c]	408293	1			T6	3875		T8	34		T11	42
valid_sources[0x3d]	383896	1			T6	3875		T8	35		T11	105
valid_sources[0x3e]	386498	1			T6	3460		T8	39		T9	1
valid_sources[0x3f]	474268	1			T6	3429		T8	18		T9	1
valid_sources[0x40]	493418	1			T6	3763		T8	58		T9	2
valid_sources[0x41]	391345	1			T6	3349		T8	27		T11	74
valid_sources[0x42]	449994	1			T6	3352		T8	44		T9	1
valid_sources[0x43]	542810	1			T6	3913		T8	41		T11	57
valid_sources[0x44]	406633	1			T6	2828		T8	32		T11	66
valid_sources[0x45]	401247	1			T6	3279		T8	36		T11	58
valid_sources[0x46]	426434	1			T1	6		T6	3319		T8	64
valid_sources[0x47]	414940	1			T6	3290		T8	59		T11	31
valid_sources[0x48]	396109	1			T4	3		T6	4018		T8	63
valid_sources[0x49]	427274	1			T6	3657		T8	38		T11	74
valid_sources[0x4a]	395358	1			T1	1		T6	3088		T8	55
valid_sources[0x4b]	399173	1			T6	3219		T8	43		T11	51
valid_sources[0x4c]	411132	1			T1	1		T6	3366		T7	5698
valid_sources[0x4d]	390720	1			T4	3		T6	2942		T8	40
valid_sources[0x4e]	396445	1			T1	1		T6	4242		T8	39
valid_sources[0x4f]	427809	1			T6	3477		T8	32		T9	3
valid_sources[0x50]	390259	1			T6	3181		T8	40		T9	1
valid_sources[0x51]	415196	1			T1	1		T4	4		T6	2909
valid_sources[0x52]	382915	1			T6	3605		T8	49		T9	1
valid_sources[0x53]	399520	1			T4	2		T6	3272		T8	59
valid_sources[0x54]	420254	1			T6	3522		T8	22		T9	2
valid_sources[0x55]	395966	1			T1	6		T4	6		T6	2753
valid_sources[0x56]	422780	1			T1	4		T6	3321		T8	56
valid_sources[0x57]	392678	1			T6	3299		T8	34		T11	70
valid_sources[0x58]	400870	1			T1	2		T6	2925		T8	42
valid_sources[0x59]	386734	1			T1	2		T6	2816		T8	28
valid_sources[0x5a]	382835	1			T1	1		T6	3616		T8	32
valid_sources[0x5b]	438892	1			T6	3309		T7	14331		T8	41
valid_sources[0x5c]	382202	1			T6	2940		T8	36		T11	65
valid_sources[0x5d]	394983	1			T6	3083		T8	48		T9	1
valid_sources[0x5e]	378233	1			T1	3		T6	3193		T8	41
valid_sources[0x5f]	396916	1			T6	4044		T8	34		T11	80
valid_sources[0x60]	403306	1			T6	3846		T8	63		T11	42
valid_sources[0x61]	402244	1			T6	3207		T8	37		T9	1
valid_sources[0x62]	415497	1			T6	3496		T8	44		T11	53
valid_sources[0x63]	398471	1			T1	1		T4	5		T5	14909
valid_sources[0x64]	391991	1			T6	3688		T8	34		T11	49
valid_sources[0x65]	418668	1			T6	3552		T8	35		T9	1
valid_sources[0x66]	403255	1			T6	3696		T8	41		T9	2
valid_sources[0x67]	383797	1			T6	4009		T8	33		T9	1
valid_sources[0x68]	391505	1			T6	3509		T8	53		T11	50
valid_sources[0x69]	406881	1			T6	3650		T8	54		T9	1
valid_sources[0x6a]	438595	1			T6	2943		T7	31740		T8	37
valid_sources[0x6b]	442988	1			T1	1		T6	3838		T8	60
valid_sources[0x6c]	404153	1			T1	4		T6	3695		T8	21
valid_sources[0x6d]	469096	1			T1	4		T4	10		T6	3547
valid_sources[0x6e]	430803	1			T4	1		T6	3759		T8	28
valid_sources[0x6f]	381738	1			T6	3412		T8	46		T9	1
valid_sources[0x70]	381758	1			T1	11		T6	3756		T8	51
valid_sources[0x71]	389654	1			T1	3		T6	3619		T8	46
valid_sources[0x72]	390231	1			T1	2		T6	4215		T8	42
valid_sources[0x73]	385609	1			T6	3860		T8	68		T11	88
valid_sources[0x74]	398463	1			T6	4182		T8	49		T11	50
valid_sources[0x75]	413865	1			T6	3895		T8	43		T9	2
valid_sources[0x76]	524909	1			T1	1		T4	31		T6	2871
valid_sources[0x77]	394161	1			T1	2		T6	3963		T8	53
valid_sources[0x78]	395734	1			T6	3207		T8	41		T11	42
valid_sources[0x79]	443931	1			T6	4023		T8	35		T11	74
valid_sources[0x7a]	421022	1			T1	1		T6	3348		T8	28
valid_sources[0x7b]	446658	1			T6	3980		T8	44		T9	2
valid_sources[0x7c]	450305	1			T6	3720		T8	79		T11	57
valid_sources[0x7d]	428640	1			T4	14		T6	3093		T8	35
valid_sources[0x7e]	394430	1			T1	1		T6	3985		T8	35
valid_sources[0x7f]	398331	1			T1	7		T6	3049		T8	30
valid_sources[0x80]	425395	1			T1	1		T6	3858		T8	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18571854

1

T1

47

T4

84

T5

16

values[0x0]

all_enables

biggest_size

4653500

1

T1

38

T2

2

T3

7

values[0x1]

all_enables

biggest_size

4599551

1

T1

17

T2

4

T3

3