Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15235162	0	0
ctrl_rd_A	2147483647	332141	0	0
intr_enable_rd_A	2147483647	292015	0	0
ovrd_rd_A	2147483647	329101	0	0
timeout_ctrl_rd_A	2147483647	328976	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15235162	0	0
T6	810861	326103	0	0
T7	312452	0	0	0
T8	94579	0	0	0
T9	669668	0	0	0
T10	73814	0	0	0
T11	186939	0	0	0
T12	139360	0	0	0
T14	0	204654	0	0
T20	0	108970	0	0
T22	0	156309	0	0
T24	102612	43398	0	0
T28	648858	0	0	0
T29	491806	0	0	0
T38	0	126752	0	0
T39	0	172421	0	0
T40	0	122607	0	0
T41	0	95086	0	0
T42	0	110623	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	332141	0	0
T20	334659	4858	0	0
T22	392756	0	0	0
T39	0	14986	0	0
T109	0	6716	0	0
T110	0	17352	0	0
T111	0	19349	0	0
T112	0	6083	0	0
T113	0	4534	0	0
T114	0	3905	0	0
T115	0	12371	0	0
T116	0	8266	0	0
T117	200390	0	0	0
T118	180570	0	0	0
T119	267000	0	0	0
T120	113397	0	0	0
T121	343682	0	0	0
T122	104853	0	0	0
T123	355811	0	0	0
T124	951919	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	292015	0	0
T16	481850	25	0	0
T20	0	3901	0	0
T23	582740	0	0	0
T33	1393	0	0	0
T39	0	13201	0	0
T109	0	5928	0	0
T110	0	15718	0	0
T111	0	17178	0	0
T112	0	5531	0	0
T113	0	4095	0	0
T114	0	3484	0	0
T115	0	10163	0	0
T125	955731	0	0	0
T126	356466	0	0	0
T127	248848	0	0	0
T128	348026	0	0	0
T129	668097	0	0	0
T130	424794	0	0	0
T131	139101	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	329101	0	0
T20	334659	4871	0	0
T22	392756	0	0	0
T39	0	15020	0	0
T109	0	6855	0	0
T110	0	16920	0	0
T111	0	18813	0	0
T112	0	6139	0	0
T113	0	5151	0	0
T114	0	3986	0	0
T115	0	11908	0	0
T116	0	7965	0	0
T117	200390	0	0	0
T118	180570	0	0	0
T119	267000	0	0	0
T120	113397	0	0	0
T121	343682	0	0	0
T122	104853	0	0	0
T123	355811	0	0	0
T124	951919	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328976	0	0
T20	334659	4843	0	0
T22	392756	0	0	0
T39	0	14858	0	0
T109	0	6864	0	0
T110	0	17216	0	0
T111	0	19366	0	0
T112	0	5934	0	0
T113	0	4430	0	0
T114	0	4085	0	0
T115	0	11756	0	0
T116	0	8551	0	0
T117	200390	0	0	0
T118	180570	0	0	0
T119	267000	0	0	0
T120	113397	0	0	0
T121	343682	0	0	0
T122	104853	0	0	0
T123	355811	0	0	0
T124	951919	0	0	0