Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	16147952	0	0
ctrl_rd_A	2147483647	279883	0	0
intr_enable_rd_A	2147483647	250347	0	0
ovrd_rd_A	2147483647	279945	0	0
timeout_ctrl_rd_A	2147483647	278829	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16147952	0	0
T5	755257	187139	0	0
T6	326792	0	0	0
T7	938602	0	0	0
T8	547609	0	0	0
T9	720	0	0	0
T10	228664	0	0	0
T11	50099	0	0	0
T12	0	303289	0	0
T13	0	222653	0	0
T15	0	70250	0	0
T16	342687	0	0	0
T20	379546	0	0	0
T21	109559	0	0	0
T28	0	102366	0	0
T29	0	177119	0	0
T30	0	86195	0	0
T31	0	30528	0	0
T32	0	81716	0	0
T33	0	343041	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	279883	0	0
T13	919138	25315	0	0
T15	249807	0	0	0
T30	0	9667	0	0
T31	0	1415	0	0
T32	0	9225	0	0
T34	374449	0	0	0
T35	341443	0	0	0
T36	264127	0	0	0
T39	0	14348	0	0
T55	0	12565	0	0
T101	0	3746	0	0
T102	0	22113	0	0
T103	0	10577	0	0
T104	0	7376	0	0
T105	228232	0	0	0
T106	953389	0	0	0
T107	869814	0	0	0
T108	142244	0	0	0
T109	484802	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	250347	0	0
T13	919138	22056	0	0
T15	249807	0	0	0
T30	0	8954	0	0
T31	0	1301	0	0
T32	0	8382	0	0
T34	374449	0	0	0
T35	341443	0	0	0
T36	264127	0	0	0
T39	0	13169	0	0
T55	0	10707	0	0
T101	0	3528	0	0
T102	0	20954	0	0
T103	0	10049	0	0
T104	0	6065	0	0
T105	228232	0	0	0
T106	953389	0	0	0
T107	869814	0	0	0
T108	142244	0	0	0
T109	484802	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	279945	0	0
T13	919138	25444	0	0
T15	249807	0	0	0
T30	0	10027	0	0
T31	0	1355	0	0
T32	0	8938	0	0
T34	374449	0	0	0
T35	341443	0	0	0
T36	264127	0	0	0
T39	0	14001	0	0
T55	0	13008	0	0
T101	0	4307	0	0
T102	0	22340	0	0
T103	0	10795	0	0
T104	0	7218	0	0
T105	228232	0	0	0
T106	953389	0	0	0
T107	869814	0	0	0
T108	142244	0	0	0
T109	484802	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	278829	0	0
T13	919138	25064	0	0
T15	249807	0	0	0
T30	0	10345	0	0
T31	0	1456	0	0
T32	0	8846	0	0
T34	374449	0	0	0
T35	341443	0	0	0
T36	264127	0	0	0
T39	0	13880	0	0
T55	0	12764	0	0
T101	0	3751	0	0
T102	0	22005	0	0
T103	0	10459	0	0
T104	0	7154	0	0
T105	228232	0	0	0
T106	953389	0	0	0
T107	869814	0	0	0
T108	142244	0	0	0
T109	484802	0	0	0