Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14649067	0	0
ctrl_rd_A	2147483647	295853	0	0
intr_enable_rd_A	2147483647	260382	0	0
ovrd_rd_A	2147483647	292030	0	0
timeout_ctrl_rd_A	2147483647	292209	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14649067	0	0
T3	849358	30839	0	0
T4	378541	0	0	0
T5	269602	0	0	0
T6	445670	153576	0	0
T7	778191	0	0	0
T8	219366	0	0	0
T9	903936	0	0	0
T10	138616	0	0	0
T11	841013	0	0	0
T15	0	141796	0	0
T19	0	138888	0	0
T20	0	81499	0	0
T22	0	202943	0	0
T31	0	60166	0	0
T32	0	32549	0	0
T33	0	185308	0	0
T34	0	71727	0	0
T35	321476	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	295853	0	0
T19	606655	15231	0	0
T20	0	9508	0	0
T31	0	6528	0	0
T33	0	9265	0	0
T40	0	11322	0	0
T42	0	6592	0	0
T96	0	2272	0	0
T97	0	20784	0	0
T98	0	8122	0	0
T99	0	16372	0	0
T100	524334	0	0	0
T101	389581	0	0	0
T102	117273	0	0	0
T103	104578	0	0	0
T104	537999	0	0	0
T105	124775	0	0	0
T106	25148	0	0	0
T107	121440	0	0	0
T108	174534	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	260382	0	0
T19	606655	13357	0	0
T20	0	8727	0	0
T31	0	5984	0	0
T33	0	7902	0	0
T40	0	10080	0	0
T42	0	5969	0	0
T96	0	1964	0	0
T100	524334	0	0	0
T101	389581	0	0	0
T102	117273	0	0	0
T103	104578	0	0	0
T104	537999	0	0	0
T105	124775	0	0	0
T106	25148	0	0	0
T107	121440	0	0	0
T108	174534	0	0	0
T109	0	11	0	0
T110	0	17	0	0
T111	0	28	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	292030	0	0
T19	606655	15462	0	0
T20	0	9754	0	0
T31	0	6587	0	0
T33	0	9031	0	0
T40	0	11289	0	0
T42	0	6768	0	0
T96	0	2022	0	0
T97	0	20794	0	0
T98	0	7957	0	0
T99	0	16145	0	0
T100	524334	0	0	0
T101	389581	0	0	0
T102	117273	0	0	0
T103	104578	0	0	0
T104	537999	0	0	0
T105	124775	0	0	0
T106	25148	0	0	0
T107	121440	0	0	0
T108	174534	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	292209	0	0
T19	606655	14951	0	0
T20	0	9160	0	0
T31	0	6793	0	0
T33	0	9274	0	0
T40	0	11124	0	0
T42	0	6490	0	0
T96	0	2165	0	0
T97	0	21419	0	0
T98	0	8254	0	0
T99	0	15669	0	0
T100	524334	0	0	0
T101	389581	0	0	0
T102	117273	0	0	0
T103	104578	0	0	0
T104	537999	0	0	0
T105	124775	0	0	0
T106	25148	0	0	0
T107	121440	0	0	0
T108	174534	0	0	0