Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14717580	0	0
ctrl_rd_A	2147483647	323295	0	0
intr_enable_rd_A	2147483647	287726	0	0
ovrd_rd_A	2147483647	322741	0	0
timeout_ctrl_rd_A	2147483647	322126	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14717580	0	0
T16	241959	0	0	0
T19	0	237168	0	0
T20	232392	0	0	0
T21	0	160697	0	0
T24	820299	138904	0	0
T31	0	106030	0	0
T32	0	55431	0	0
T33	0	237994	0	0
T34	0	142676	0	0
T35	0	108440	0	0
T36	0	229525	0	0
T37	0	125915	0	0
T38	36939	0	0	0
T39	462676	0	0	0
T40	737016	0	0	0
T41	66405	0	0	0
T42	124864	0	0	0
T43	7967	0	0	0
T44	162560	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	323295	0	0
T16	241959	0	0	0
T19	0	26236	0	0
T20	232392	0	0	0
T24	820299	9522	0	0
T38	36939	0	0	0
T39	462676	0	0	0
T40	737016	0	0	0
T41	66405	0	0	0
T42	124864	0	0	0
T43	7967	0	0	0
T44	162560	0	0	0
T54	0	5973	0	0
T57	0	5480	0	0
T59	0	14344	0	0
T101	0	8781	0	0
T106	0	7334	0	0
T107	0	4282	0	0
T108	0	11792	0	0
T109	0	5752	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	287726	0	0
T9	387519	10	0	0
T10	31294	0	0	0
T11	98069	0	0	0
T12	117745	0	0	0
T13	120754	0	0	0
T14	263913	0	0	0
T15	125319	0	0	0
T19	0	23381	0	0
T23	468783	0	0	0
T24	0	8745	0	0
T45	735268	0	0	0
T54	0	5224	0	0
T57	0	4912	0	0
T59	0	12074	0	0
T101	0	8286	0	0
T106	0	6934	0	0
T107	0	3932	0	0
T110	0	10	0	0
T111	222158	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	322741	0	0
T16	241959	0	0	0
T19	0	26185	0	0
T20	232392	0	0	0
T24	820299	9895	0	0
T38	36939	0	0	0
T39	462676	0	0	0
T40	737016	0	0	0
T41	66405	0	0	0
T42	124864	0	0	0
T43	7967	0	0	0
T44	162560	0	0	0
T54	0	5697	0	0
T57	0	5495	0	0
T59	0	13388	0	0
T101	0	9164	0	0
T106	0	7445	0	0
T107	0	4755	0	0
T108	0	11459	0	0
T109	0	5694	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	322126	0	0
T16	241959	0	0	0
T19	0	27232	0	0
T20	232392	0	0	0
T24	820299	9607	0	0
T38	36939	0	0	0
T39	462676	0	0	0
T40	737016	0	0	0
T41	66405	0	0	0
T42	124864	0	0	0
T43	7967	0	0	0
T44	162560	0	0	0
T54	0	5671	0	0
T57	0	5661	0	0
T59	0	14177	0	0
T101	0	8598	0	0
T106	0	7307	0	0
T107	0	4212	0	0
T108	0	11670	0	0
T109	0	5907	0	0