Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 73154459 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 29671537 1 T1 43186 T2 11 T3 71



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 92082086 1 T1 195434 T2 32 T3 875
values[0x0] 5078286 1 T1 875 T2 6 T3 57
values[0x1] 5665624 1 T1 808 T2 7 T3 36



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 50685611 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 52140385 1 T1 88786 T2 20 T3 348



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 339760 1 T1 665 T3 6 T4 247
valid_sources[0x01] 393058 1 T1 169 T3 2 T4 246
valid_sources[0x02] 389967 1 T1 673 T3 4 T4 259
valid_sources[0x03] 417648 1 T1 397 T3 4 T4 266
valid_sources[0x04] 387421 1 T1 510 T3 4 T4 265
valid_sources[0x05] 387294 1 T1 555 T3 5 T4 277
valid_sources[0x06] 426689 1 T1 353 T3 7 T4 268
valid_sources[0x07] 520415 1 T1 448 T3 6 T4 268
valid_sources[0x08] 388538 1 T1 463 T2 1 T3 7
valid_sources[0x09] 368180 1 T1 323 T3 1 T4 276
valid_sources[0x0a] 381344 1 T1 639 T3 4 T4 256
valid_sources[0x0b] 387397 1 T1 875 T3 8 T4 225
valid_sources[0x0c] 403408 1 T1 465 T3 7 T4 265
valid_sources[0x0d] 437955 1 T1 658 T3 2 T4 264
valid_sources[0x0e] 388471 1 T1 616 T3 2 T4 272
valid_sources[0x0f] 375097 1 T1 213 T2 1 T3 1
valid_sources[0x10] 434003 1 T1 127 T3 1 T4 254
valid_sources[0x11] 363156 1 T1 639 T3 6 T4 298
valid_sources[0x12] 396064 1 T1 309 T3 2 T4 265
valid_sources[0x13] 430988 1 T1 262 T3 1 T4 222
valid_sources[0x14] 375496 1 T1 372 T3 6 T4 267
valid_sources[0x15] 376737 1 T1 794 T3 5 T4 269
valid_sources[0x16] 374522 1 T1 584 T3 6 T4 270
valid_sources[0x17] 408160 1 T1 805 T3 2 T4 245
valid_sources[0x18] 377318 1 T1 858 T3 1 T4 268
valid_sources[0x19] 412654 1 T1 197 T3 3 T4 267
valid_sources[0x1a] 380856 1 T1 360 T2 1 T3 3
valid_sources[0x1b] 394156 1 T1 1045 T2 1 T3 5
valid_sources[0x1c] 424875 1 T1 1092 T2 1 T3 6
valid_sources[0x1d] 498377 1 T1 514 T3 1 T4 260
valid_sources[0x1e] 392852 1 T1 708 T3 3 T4 237
valid_sources[0x1f] 355270 1 T1 610 T3 6 T4 254
valid_sources[0x20] 400350 1 T1 147 T3 3 T4 244
valid_sources[0x21] 387151 1 T1 1090 T3 2 T4 230
valid_sources[0x22] 577299 1 T1 1095 T3 5 T4 245
valid_sources[0x23] 383255 1 T1 383 T3 1 T4 278
valid_sources[0x24] 448630 1 T1 327 T3 2 T4 242
valid_sources[0x25] 424395 1 T1 289 T3 2 T4 288
valid_sources[0x26] 370998 1 T1 571 T3 6 T4 245
valid_sources[0x27] 373998 1 T1 478 T3 3 T4 242
valid_sources[0x28] 397185 1 T1 477 T2 1 T3 2
valid_sources[0x29] 375415 1 T1 558 T3 4 T4 242
valid_sources[0x2a] 384588 1 T1 697 T3 4 T4 278
valid_sources[0x2b] 395457 1 T1 224 T3 6 T4 276
valid_sources[0x2c] 388360 1 T1 388 T3 2 T4 239
valid_sources[0x2d] 390825 1 T1 269 T3 2 T4 285
valid_sources[0x2e] 386426 1 T1 594 T3 4 T4 221
valid_sources[0x2f] 411764 1 T1 592 T3 4 T4 291
valid_sources[0x30] 404300 1 T1 267 T3 4 T4 293
valid_sources[0x31] 384327 1 T1 175 T3 4 T4 276
valid_sources[0x32] 363332 1 T1 418 T2 2 T3 4
valid_sources[0x33] 391370 1 T1 447 T3 4 T4 271
valid_sources[0x34] 385878 1 T1 698 T3 2 T4 271
valid_sources[0x35] 383060 1 T1 565 T3 2 T4 237
valid_sources[0x36] 407483 1 T1 388 T2 1 T3 5
valid_sources[0x37] 390715 1 T1 812 T3 8 T4 292
valid_sources[0x38] 400215 1 T1 583 T3 2 T4 244
valid_sources[0x39] 413368 1 T1 550 T3 1 T4 250
valid_sources[0x3a] 447533 1 T1 332 T3 6 T4 271
valid_sources[0x3b] 390883 1 T1 451 T3 1 T4 253
valid_sources[0x3c] 371127 1 T1 493 T3 1 T4 239
valid_sources[0x3d] 394621 1 T1 658 T3 3 T4 261
valid_sources[0x3e] 392629 1 T1 300 T3 1 T4 268
valid_sources[0x3f] 380429 1 T1 619 T3 2 T4 262
valid_sources[0x40] 393243 1 T1 564 T3 9 T4 244
valid_sources[0x41] 393983 1 T1 344 T3 1 T4 253
valid_sources[0x42] 368370 1 T1 186 T3 2 T4 264
valid_sources[0x43] 395557 1 T1 511 T3 2 T4 287
valid_sources[0x44] 373243 1 T1 483 T3 8 T4 250
valid_sources[0x45] 372732 1 T1 1142 T3 3 T4 274
valid_sources[0x46] 440463 1 T1 702 T2 1 T3 4
valid_sources[0x47] 380982 1 T1 576 T3 2 T4 250
valid_sources[0x48] 351556 1 T1 447 T3 7 T4 269
valid_sources[0x49] 429694 1 T1 682 T2 1 T3 1
valid_sources[0x4a] 381436 1 T1 371 T3 5 T4 259
valid_sources[0x4b] 376372 1 T1 222 T2 1 T3 7
valid_sources[0x4c] 368607 1 T1 600 T3 5 T4 262
valid_sources[0x4d] 417286 1 T1 269 T3 5 T4 277
valid_sources[0x4e] 388495 1 T1 376 T3 1 T4 231
valid_sources[0x4f] 378370 1 T1 678 T3 3 T4 247
valid_sources[0x50] 395953 1 T1 398 T3 4 T4 229
valid_sources[0x51] 387033 1 T1 130 T3 2 T4 273
valid_sources[0x52] 380371 1 T1 627 T3 3 T4 271
valid_sources[0x53] 366920 1 T1 376 T3 4 T4 271
valid_sources[0x54] 477506 1 T1 417 T2 1 T4 242
valid_sources[0x55] 484166 1 T1 370 T3 2 T4 277
valid_sources[0x56] 395292 1 T1 579 T3 3 T4 264
valid_sources[0x57] 383718 1 T1 461 T2 1 T3 8
valid_sources[0x58] 483476 1 T1 193 T2 1 T3 4
valid_sources[0x59] 502565 1 T1 419 T3 1 T4 254
valid_sources[0x5a] 389072 1 T1 930 T3 6 T4 234
valid_sources[0x5b] 383028 1 T1 331 T4 267 T9 49
valid_sources[0x5c] 420890 1 T1 565 T3 3 T4 243
valid_sources[0x5d] 401008 1 T1 420 T3 6 T4 267
valid_sources[0x5e] 366809 1 T1 411 T3 2 T4 239
valid_sources[0x5f] 377999 1 T1 362 T3 2 T4 279
valid_sources[0x60] 404068 1 T1 21400 T3 4 T4 267
valid_sources[0x61] 383003 1 T1 610 T2 2 T3 3
valid_sources[0x62] 487028 1 T1 192 T3 9 T4 247
valid_sources[0x63] 420998 1 T1 442 T3 2 T4 253
valid_sources[0x64] 369892 1 T1 589 T3 9 T4 243
valid_sources[0x65] 471445 1 T1 361 T3 5 T4 289
valid_sources[0x66] 361956 1 T1 402 T2 1 T3 6
valid_sources[0x67] 369270 1 T1 307 T3 2 T4 260
valid_sources[0x68] 420793 1 T1 269 T2 1 T3 5
valid_sources[0x69] 468956 1 T1 402 T3 7 T4 273
valid_sources[0x6a] 400710 1 T1 342 T3 3 T4 224
valid_sources[0x6b] 360823 1 T1 663 T3 7 T4 258
valid_sources[0x6c] 385721 1 T1 410 T3 3 T4 291
valid_sources[0x6d] 374584 1 T1 459 T3 4 T4 269
valid_sources[0x6e] 470987 1 T1 189 T3 4 T4 228
valid_sources[0x6f] 525873 1 T1 634 T3 3 T4 286
valid_sources[0x70] 387794 1 T1 489 T3 4 T4 236
valid_sources[0x71] 368898 1 T1 611 T3 4 T4 259
valid_sources[0x72] 425715 1 T1 548 T3 2 T4 282
valid_sources[0x73] 451735 1 T1 364 T3 5 T4 235
valid_sources[0x74] 433000 1 T1 583 T3 6 T4 247
valid_sources[0x75] 365243 1 T1 539 T2 1 T3 1
valid_sources[0x76] 437159 1 T1 531 T3 4 T4 264
valid_sources[0x77] 390722 1 T1 163 T3 3 T4 246
valid_sources[0x78] 414772 1 T1 550 T3 6 T4 277
valid_sources[0x79] 424071 1 T1 649 T3 1 T4 279
valid_sources[0x7a] 396823 1 T1 565 T3 5 T4 266
valid_sources[0x7b] 406788 1 T1 506 T2 2 T3 5
valid_sources[0x7c] 402392 1 T1 523 T3 5 T4 256
valid_sources[0x7d] 398262 1 T1 330 T3 4 T4 250
valid_sources[0x7e] 379338 1 T1 236 T3 4 T4 233
valid_sources[0x7f] 522458 1 T1 349 T2 1 T3 6
valid_sources[0x80] 391532 1 T1 109 T3 2 T4 252



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 20103950 1 T1 42772 T2 6 T3 8
values[0x0] all_enables biggest_size 4813086 1 T1 269 T2 3 T3 39
values[0x1] all_enables biggest_size 4754501 1 T1 145 T2 2 T3 24

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%