Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15752192	0	0
ctrl_rd_A	2147483647	342613	0	0
intr_enable_rd_A	2147483647	302906	0	0
ovrd_rd_A	2147483647	339216	0	0
timeout_ctrl_rd_A	2147483647	341981	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15752192	0	0
T12	850557	0	0	0
T14	525013	208877	0	0
T15	117490	0	0	0
T16	680747	0	0	0
T18	28591	0	0	0
T21	0	204855	0	0
T24	0	76690	0	0
T25	0	315501	0	0
T33	0	175115	0	0
T34	0	122882	0	0
T35	0	40418	0	0
T36	0	210992	0	0
T37	0	252814	0	0
T38	0	139270	0	0
T39	883566	0	0	0
T40	280769	0	0	0
T41	71663	0	0	0
T42	176446	0	0	0
T43	40501	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	342613	0	0
T20	110633	0	0	0
T22	214743	0	0	0
T24	316218	8270	0	0
T25	840242	0	0	0
T28	812	0	0	0
T34	0	3807	0	0
T35	0	4827	0	0
T37	0	6927	0	0
T44	123165	0	0	0
T50	0	3482	0	0
T53	0	3262	0	0
T60	0	10702	0	0
T107	0	19715	0	0
T108	0	14929	0	0
T109	0	22250	0	0
T110	473697	0	0	0
T111	110656	0	0	0
T112	181973	0	0	0
T113	51983	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	302906	0	0
T20	110633	0	0	0
T22	214743	0	0	0
T24	316218	7417	0	0
T25	840242	0	0	0
T28	812	0	0	0
T34	0	3287	0	0
T35	0	3963	0	0
T37	0	6036	0	0
T44	123165	0	0	0
T50	0	3402	0	0
T53	0	3052	0	0
T60	0	9370	0	0
T107	0	17967	0	0
T108	0	13677	0	0
T110	473697	0	0	0
T111	110656	0	0	0
T112	181973	0	0	0
T113	51983	0	0	0
T114	0	34	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	339216	0	0
T20	110633	0	0	0
T22	214743	0	0	0
T24	316218	8411	0	0
T25	840242	0	0	0
T28	812	0	0	0
T34	0	3814	0	0
T35	0	4402	0	0
T37	0	7090	0	0
T44	123165	0	0	0
T50	0	3584	0	0
T53	0	3070	0	0
T60	0	10553	0	0
T107	0	20128	0	0
T108	0	15738	0	0
T109	0	21687	0	0
T110	473697	0	0	0
T111	110656	0	0	0
T112	181973	0	0	0
T113	51983	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	341981	0	0
T20	110633	0	0	0
T22	214743	0	0	0
T24	316218	8241	0	0
T25	840242	0	0	0
T28	812	0	0	0
T34	0	3633	0	0
T35	0	4861	0	0
T37	0	6988	0	0
T44	123165	0	0	0
T50	0	3550	0	0
T53	0	3120	0	0
T60	0	10965	0	0
T107	0	20091	0	0
T108	0	15647	0	0
T109	0	21507	0	0
T110	473697	0	0	0
T111	110656	0	0	0
T112	181973	0	0	0
T113	51983	0	0	0