Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14575938	0	0
ctrl_rd_A	2147483647	234088	0	0
intr_enable_rd_A	2147483647	208209	0	0
ovrd_rd_A	2147483647	232178	0	0
timeout_ctrl_rd_A	2147483647	231944	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14575938	0	0
T4	918563	23403	0	0
T5	656053	0	0	0
T6	1399	0	0	0
T7	141072	0	0	0
T8	490986	202136	0	0
T9	409514	0	0	0
T10	646584	0	0	0
T11	353035	0	0	0
T12	203290	67588	0	0
T16	0	152339	0	0
T17	0	276338	0	0
T24	0	58228	0	0
T25	668	0	0	0
T30	0	144324	0	0
T31	0	189028	0	0
T32	0	86226	0	0
T33	0	225065	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	234088	0	0
T4	918563	2577	0	0
T5	656053	0	0	0
T6	1399	0	0	0
T7	141072	0	0	0
T8	490986	0	0	0
T9	409514	0	0	0
T10	646584	0	0	0
T11	353035	0	0	0
T12	203290	0	0	0
T25	668	0	0	0
T33	0	10688	0	0
T50	0	7544	0	0
T108	0	7658	0	0
T109	0	5713	0	0
T110	0	3878	0	0
T111	0	3651	0	0
T112	0	5664	0	0
T113	0	7143	0	0
T114	0	3461	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	208209	0	0
T4	918563	2212	0	0
T5	656053	0	0	0
T6	1399	0	0	0
T7	141072	0	0	0
T8	490986	0	0	0
T9	409514	0	0	0
T10	646584	0	0	0
T11	353035	0	0	0
T12	203290	0	0	0
T25	668	0	0	0
T33	0	9866	0	0
T50	0	6918	0	0
T108	0	6550	0	0
T109	0	4995	0	0
T110	0	3421	0	0
T111	0	3310	0	0
T112	0	4768	0	0
T113	0	6199	0	0
T115	0	22	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	232178	0	0
T4	918563	2602	0	0
T5	656053	0	0	0
T6	1399	0	0	0
T7	141072	0	0	0
T8	490986	0	0	0
T9	409514	0	0	0
T10	646584	0	0	0
T11	353035	0	0	0
T12	203290	0	0	0
T25	668	0	0	0
T33	0	11354	0	0
T50	0	7840	0	0
T108	0	7728	0	0
T109	0	5753	0	0
T110	0	3650	0	0
T111	0	3538	0	0
T112	0	5424	0	0
T113	0	6930	0	0
T114	0	3404	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	231944	0	0
T4	918563	2486	0	0
T5	656053	0	0	0
T6	1399	0	0	0
T7	141072	0	0	0
T8	490986	0	0	0
T9	409514	0	0	0
T10	646584	0	0	0
T11	353035	0	0	0
T12	203290	0	0	0
T25	668	0	0	0
T33	0	10543	0	0
T50	0	8016	0	0
T108	0	7143	0	0
T109	0	5574	0	0
T110	0	3755	0	0
T111	0	3554	0	0
T112	0	5488	0	0
T113	0	7018	0	0
T114	0	3472	0	0