Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 73677275 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 29495183 1 T1 46 T2 351 T3 16



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 92582026 1 T1 31 T2 570 T3 1923
values[0x0] 5003513 1 T1 35 T2 109 T3 5
values[0x1] 5586919 1 T1 40 T2 117 T3 8



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 51029872 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 52142586 1 T1 51 T2 415 T3 648



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 433426 1 T3 10 T5 39 T7 21
valid_sources[0x01] 378012 1 T3 4 T5 48 T7 12
valid_sources[0x02] 424451 1 T2 7 T3 7 T5 50
valid_sources[0x03] 362990 1 T3 5 T4 9 T5 49
valid_sources[0x04] 384455 1 T3 9 T5 38 T7 32
valid_sources[0x05] 381619 1 T3 4 T5 38 T7 11
valid_sources[0x06] 381783 1 T2 11 T3 7 T5 52
valid_sources[0x07] 414833 1 T1 1 T2 9 T3 13
valid_sources[0x08] 374073 1 T3 10 T5 48 T6 1
valid_sources[0x09] 401885 1 T3 9 T5 51 T7 10
valid_sources[0x0a] 442586 1 T3 8 T4 24 T5 37
valid_sources[0x0b] 435934 1 T1 1 T3 3 T5 49
valid_sources[0x0c] 385916 1 T2 3 T3 4 T5 40
valid_sources[0x0d] 438642 1 T3 12 T5 47 T7 12
valid_sources[0x0e] 398520 1 T2 4 T3 5 T5 43
valid_sources[0x0f] 399703 1 T3 11 T5 46 T7 15
valid_sources[0x10] 411882 1 T3 7 T5 44 T7 23
valid_sources[0x11] 377167 1 T1 1 T2 4 T3 8
valid_sources[0x12] 407272 1 T3 5 T5 47 T7 9
valid_sources[0x13] 378736 1 T2 19 T3 4 T5 30
valid_sources[0x14] 486536 1 T3 9 T5 50 T6 75
valid_sources[0x15] 498243 1 T1 2 T2 3 T3 8
valid_sources[0x16] 382917 1 T3 6 T5 49 T7 9
valid_sources[0x17] 448509 1 T3 7 T5 44 T7 16
valid_sources[0x18] 395974 1 T3 12 T5 56 T6 387
valid_sources[0x19] 417065 1 T3 10 T5 42 T7 5
valid_sources[0x1a] 407628 1 T3 7 T5 56 T7 17
valid_sources[0x1b] 448468 1 T1 2 T3 14 T5 41
valid_sources[0x1c] 389807 1 T1 3 T3 5 T5 68
valid_sources[0x1d] 378663 1 T2 16 T3 8 T5 40
valid_sources[0x1e] 518682 1 T2 23 T3 3 T5 40
valid_sources[0x1f] 538527 1 T1 1 T3 9 T5 64
valid_sources[0x20] 381156 1 T3 8 T5 39 T7 18
valid_sources[0x21] 382780 1 T3 9 T4 3 T5 35
valid_sources[0x22] 373212 1 T3 7 T4 69 T5 61
valid_sources[0x23] 398834 1 T3 13 T5 48 T7 16
valid_sources[0x24] 448626 1 T3 8 T5 43 T7 21
valid_sources[0x25] 405233 1 T3 5 T4 4 T5 43
valid_sources[0x26] 359767 1 T1 3 T2 3 T3 6
valid_sources[0x27] 385540 1 T1 2 T3 4 T5 48
valid_sources[0x28] 405969 1 T3 13 T5 44 T7 24
valid_sources[0x29] 536127 1 T3 4 T5 50 T7 9
valid_sources[0x2a] 550130 1 T1 1 T2 9 T3 7
valid_sources[0x2b] 380148 1 T2 7 T3 6 T5 37
valid_sources[0x2c] 371648 1 T3 2 T4 18 T5 35
valid_sources[0x2d] 396732 1 T2 9 T3 5 T5 45
valid_sources[0x2e] 381319 1 T2 1 T3 15 T5 38
valid_sources[0x2f] 389909 1 T1 1 T3 11 T5 51
valid_sources[0x30] 463593 1 T3 6 T5 40 T7 25
valid_sources[0x31] 395919 1 T2 27 T3 8 T5 39
valid_sources[0x32] 397001 1 T2 7 T3 11 T4 20
valid_sources[0x33] 421107 1 T1 1 T3 11 T5 59
valid_sources[0x34] 390495 1 T3 8 T5 40 T7 20
valid_sources[0x35] 382626 1 T3 9 T5 44 T7 12
valid_sources[0x36] 385829 1 T1 1 T3 10 T5 57
valid_sources[0x37] 375259 1 T2 6 T3 8 T5 47
valid_sources[0x38] 402786 1 T2 6 T3 12 T5 44
valid_sources[0x39] 463688 1 T3 3 T5 31 T7 18
valid_sources[0x3a] 359635 1 T1 1 T3 7 T4 55
valid_sources[0x3b] 399977 1 T2 2 T3 6 T5 37
valid_sources[0x3c] 378673 1 T1 1 T3 7 T5 32
valid_sources[0x3d] 371335 1 T3 7 T5 36 T7 3
valid_sources[0x3e] 362009 1 T2 6 T3 12 T5 53
valid_sources[0x3f] 392406 1 T3 2 T5 41 T7 22
valid_sources[0x40] 377074 1 T3 3 T4 89 T5 38
valid_sources[0x41] 370486 1 T2 1 T3 13 T5 39
valid_sources[0x42] 439725 1 T3 4 T5 44 T7 29
valid_sources[0x43] 386156 1 T3 4 T5 50 T7 20
valid_sources[0x44] 413984 1 T2 11 T3 11 T5 36
valid_sources[0x45] 424655 1 T3 5 T5 49 T7 27
valid_sources[0x46] 435149 1 T1 1 T2 4 T3 8
valid_sources[0x47] 386563 1 T2 19 T3 6 T5 43
valid_sources[0x48] 462917 1 T3 10 T5 39 T6 196
valid_sources[0x49] 380860 1 T3 7 T5 32 T6 149
valid_sources[0x4a] 381674 1 T2 8 T3 8 T5 37
valid_sources[0x4b] 396465 1 T2 2 T3 10 T5 36
valid_sources[0x4c] 378924 1 T2 3 T3 5 T5 56
valid_sources[0x4d] 374357 1 T3 10 T5 52 T7 11
valid_sources[0x4e] 385162 1 T3 6 T5 41 T7 16
valid_sources[0x4f] 373658 1 T3 4 T4 27 T5 43
valid_sources[0x50] 426420 1 T1 1 T3 6 T5 48
valid_sources[0x51] 409799 1 T3 8 T5 38 T6 619
valid_sources[0x52] 397515 1 T2 1 T3 9 T5 47
valid_sources[0x53] 370954 1 T3 9 T5 43 T7 6
valid_sources[0x54] 400440 1 T1 2 T3 11 T5 34
valid_sources[0x55] 412106 1 T2 10 T3 14 T5 38
valid_sources[0x56] 507995 1 T3 6 T5 29 T7 12
valid_sources[0x57] 406309 1 T1 1 T2 9 T3 6
valid_sources[0x58] 401296 1 T2 5 T3 8 T5 41
valid_sources[0x59] 381321 1 T3 9 T4 22 T5 29
valid_sources[0x5a] 413687 1 T2 24 T3 10 T5 41
valid_sources[0x5b] 376816 1 T3 11 T5 42 T7 18
valid_sources[0x5c] 383324 1 T2 6 T3 3 T5 50
valid_sources[0x5d] 399136 1 T3 12 T5 39 T7 15
valid_sources[0x5e] 378736 1 T3 8 T5 42 T7 17
valid_sources[0x5f] 402889 1 T2 1 T3 12 T5 51
valid_sources[0x60] 381977 1 T1 2 T2 15 T3 5
valid_sources[0x61] 392218 1 T1 1 T3 8 T5 46
valid_sources[0x62] 457965 1 T3 6 T4 55 T5 57
valid_sources[0x63] 427695 1 T1 1 T3 5 T5 57
valid_sources[0x64] 375214 1 T3 8 T5 45 T7 8
valid_sources[0x65] 508970 1 T3 11 T5 42 T7 35
valid_sources[0x66] 393805 1 T1 2 T2 4 T3 7
valid_sources[0x67] 395009 1 T1 2 T2 17 T3 11
valid_sources[0x68] 382250 1 T1 2 T3 5 T5 45
valid_sources[0x69] 386269 1 T3 7 T5 34 T7 11
valid_sources[0x6a] 386917 1 T1 1 T2 6 T3 8
valid_sources[0x6b] 395163 1 T3 11 T5 31 T7 18
valid_sources[0x6c] 414112 1 T1 1 T2 16 T3 5
valid_sources[0x6d] 378549 1 T1 1 T3 13 T5 34
valid_sources[0x6e] 372673 1 T1 2 T2 5 T3 3
valid_sources[0x6f] 369281 1 T1 1 T2 5 T3 8
valid_sources[0x70] 383835 1 T3 9 T5 54 T7 21
valid_sources[0x71] 368210 1 T1 1 T3 7 T5 56
valid_sources[0x72] 379997 1 T1 1 T3 3 T5 46
valid_sources[0x73] 420184 1 T2 6 T3 5 T4 4
valid_sources[0x74] 382645 1 T1 2 T2 11 T3 6
valid_sources[0x75] 364377 1 T2 19 T3 8 T5 53
valid_sources[0x76] 410273 1 T3 6 T5 44 T7 10
valid_sources[0x77] 376723 1 T1 3 T3 9 T5 41
valid_sources[0x78] 396908 1 T1 3 T3 3 T5 37
valid_sources[0x79] 382543 1 T3 9 T4 119 T5 43
valid_sources[0x7a] 389331 1 T3 5 T4 69 T5 45
valid_sources[0x7b] 384588 1 T2 1 T3 9 T5 41
valid_sources[0x7c] 377054 1 T2 13 T3 9 T5 31
valid_sources[0x7d] 554138 1 T3 4 T4 1 T5 42
valid_sources[0x7e] 398869 1 T3 7 T5 49 T7 12
valid_sources[0x7f] 370651 1 T1 1 T2 18 T3 3
valid_sources[0x80] 432989 1 T1 1 T2 14 T3 6



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 20115498 1 T1 16 T2 295 T3 10
values[0x0] all_enables biggest_size 4720610 1 T1 15 T2 37 T3 2
values[0x1] all_enables biggest_size 4659075 1 T1 15 T2 19 T3 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%