Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15584329	0	0
ctrl_rd_A	2147483647	208557	0	0
intr_enable_rd_A	2147483647	183334	0	0
ovrd_rd_A	2147483647	206752	0	0
timeout_ctrl_rd_A	2147483647	208469	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15584329	0	0
T25	118046	415651	0	0
T26	237430	100647	0	0
T27	0	117166	0	0
T32	1119	0	0	0
T36	0	37426	0	0
T37	0	57571	0	0
T38	0	294987	0	0
T39	0	41851	0	0
T40	0	242400	0	0
T41	0	132777	0	0
T42	0	89982	0	0
T43	847267	0	0	0
T44	356264	0	0	0
T45	213682	0	0	0
T46	102576	0	0	0
T47	730194	0	0	0
T48	46018	0	0	0
T49	218564	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	208557	0	0
T39	181274	4756	0	0
T41	0	15394	0	0
T63	0	9924	0	0
T64	0	9780	0	0
T66	0	11025	0	0
T67	0	3054	0	0
T113	0	14091	0	0
T114	0	4612	0	0
T115	0	8118	0	0
T116	0	21468	0	0
T117	955	0	0	0
T118	138775	0	0	0
T119	359413	0	0	0
T120	252251	0	0	0
T121	132634	0	0	0
T122	482509	0	0	0
T123	512156	0	0	0
T124	193363	0	0	0
T125	590273	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	183334	0	0
T21	195704	0	0	0
T27	316784	0	0	0
T39	0	4368	0	0
T41	0	13786	0	0
T63	0	8655	0	0
T64	0	8614	0	0
T66	0	9224	0	0
T67	0	2697	0	0
T92	561663	18	0	0
T113	0	12285	0	0
T114	0	4316	0	0
T126	0	13	0	0
T127	883098	0	0	0
T128	212110	0	0	0
T129	149977	0	0	0
T130	174008	0	0	0
T131	312040	0	0	0
T132	208301	0	0	0
T133	148720	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	206752	0	0
T39	181274	4960	0	0
T41	0	15873	0	0
T63	0	9650	0	0
T64	0	9847	0	0
T66	0	10383	0	0
T67	0	2899	0	0
T113	0	13994	0	0
T114	0	4890	0	0
T115	0	7809	0	0
T116	0	21354	0	0
T117	955	0	0	0
T118	138775	0	0	0
T119	359413	0	0	0
T120	252251	0	0	0
T121	132634	0	0	0
T122	482509	0	0	0
T123	512156	0	0	0
T124	193363	0	0	0
T125	590273	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	208469	0	0
T39	181274	4697	0	0
T41	0	15569	0	0
T63	0	9543	0	0
T64	0	9885	0	0
T66	0	10556	0	0
T67	0	2915	0	0
T113	0	13966	0	0
T114	0	4683	0	0
T115	0	8127	0	0
T116	0	21670	0	0
T117	955	0	0	0
T118	138775	0	0	0
T119	359413	0	0	0
T120	252251	0	0	0
T121	132634	0	0	0
T122	482509	0	0	0
T123	512156	0	0	0
T124	193363	0	0	0
T125	590273	0	0	0