Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13668667	0	0
ctrl_rd_A	2147483647	228470	0	0
intr_enable_rd_A	2147483647	200489	0	0
ovrd_rd_A	2147483647	225323	0	0
timeout_ctrl_rd_A	2147483647	227558	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13668667	0	0
T6	163256	38292	0	0
T7	113768	0	0	0
T8	880793	0	0	0
T9	747156	0	0	0
T10	106192	0	0	0
T11	190770	0	0	0
T12	438436	0	0	0
T16	49474	0	0	0
T27	0	88741	0	0
T28	0	40445	0	0
T35	0	64070	0	0
T36	0	226529	0	0
T37	0	175461	0	0
T38	0	273277	0	0
T39	0	185798	0	0
T40	0	37723	0	0
T41	0	256921	0	0
T42	576476	0	0	0
T43	499608	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	228470	0	0
T6	163256	4111	0	0
T7	113768	0	0	0
T8	880793	0	0	0
T9	747156	0	0	0
T10	106192	0	0	0
T11	190770	0	0	0
T12	438436	0	0	0
T16	49474	0	0	0
T27	0	10139	0	0
T28	0	4740	0	0
T38	0	30804	0	0
T40	0	2051	0	0
T41	0	27759	0	0
T42	576476	0	0	0
T43	499608	0	0	0
T59	0	3807	0	0
T109	0	12113	0	0
T110	0	1761	0	0
T111	0	14825	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	200489	0	0
T6	163256	3538	0	0
T7	113768	0	0	0
T8	880793	0	0	0
T9	747156	0	0	0
T10	106192	0	0	0
T11	190770	0	0	0
T12	438436	0	0	0
T15	0	7	0	0
T16	49474	0	0	0
T27	0	9047	0	0
T28	0	4151	0	0
T38	0	26997	0	0
T40	0	1813	0	0
T41	0	25264	0	0
T42	576476	0	0	0
T43	499608	0	0	0
T109	0	10087	0	0
T110	0	1490	0	0
T112	0	25	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	225323	0	0
T6	163256	4140	0	0
T7	113768	0	0	0
T8	880793	0	0	0
T9	747156	0	0	0
T10	106192	0	0	0
T11	190770	0	0	0
T12	438436	0	0	0
T16	49474	0	0	0
T27	0	10101	0	0
T28	0	4633	0	0
T38	0	30394	0	0
T40	0	2179	0	0
T41	0	28110	0	0
T42	576476	0	0	0
T43	499608	0	0	0
T59	0	3707	0	0
T109	0	11787	0	0
T110	0	1529	0	0
T111	0	14932	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	227558	0	0
T6	163256	4056	0	0
T7	113768	0	0	0
T8	880793	0	0	0
T9	747156	0	0	0
T10	106192	0	0	0
T11	190770	0	0	0
T12	438436	0	0	0
T16	49474	0	0	0
T27	0	9993	0	0
T28	0	4650	0	0
T38	0	31029	0	0
T40	0	2187	0	0
T41	0	28989	0	0
T42	576476	0	0	0
T43	499608	0	0	0
T59	0	3564	0	0
T109	0	12135	0	0
T110	0	1569	0	0
T111	0	14641	0	0