Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	76083791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29402778

1

T1

13

T2

143

T3

99

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	95097250	1			T1	2186		T2	62814		T3	1057
values[0x0]	4911346	1			T1	6		T2	164		T3	122
values[0x1]	5477973	1			T1	7		T2	172		T3	109

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52710219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52776350

1

T1

759

T2

20936

T3

427

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	403396	1			T1	5		T3	6		T5	4
valid_sources[0x01]	407979	1			T1	13		T3	6		T5	5
valid_sources[0x02]	419474	1			T3	3		T5	6		T6	5
valid_sources[0x03]	415088	1			T3	8		T5	1		T6	16
valid_sources[0x04]	485489	1			T1	28		T3	10		T5	1
valid_sources[0x05]	412461	1			T3	6		T6	3		T7	14
valid_sources[0x06]	393298	1			T3	1		T5	2		T6	19
valid_sources[0x07]	392627	1			T3	7		T5	5		T6	17
valid_sources[0x08]	421296	1			T1	28		T3	7		T5	2
valid_sources[0x09]	414483	1			T3	2		T5	3		T6	5
valid_sources[0x0a]	406269	1			T1	3		T3	6		T5	1
valid_sources[0x0b]	414016	1			T1	5		T3	6		T5	2
valid_sources[0x0c]	411491	1			T1	17		T3	2		T5	4
valid_sources[0x0d]	411634	1			T3	2		T6	10		T7	9
valid_sources[0x0e]	442255	1			T3	2		T6	24		T7	4
valid_sources[0x0f]	395322	1			T3	6		T5	1		T6	8
valid_sources[0x10]	398692	1			T1	20		T3	2		T5	9
valid_sources[0x11]	413550	1			T3	5		T5	7		T6	8
valid_sources[0x12]	400593	1			T3	5		T5	5		T6	16
valid_sources[0x13]	395136	1			T3	5		T5	2		T6	15
valid_sources[0x14]	461059	1			T1	42		T3	1		T5	5
valid_sources[0x15]	404630	1			T3	6		T5	5		T6	12
valid_sources[0x16]	393446	1			T3	5		T5	6		T6	12
valid_sources[0x17]	400095	1			T3	5		T5	4		T6	10
valid_sources[0x18]	395039	1			T1	26		T3	9		T5	5
valid_sources[0x19]	378956	1			T1	3		T3	5		T5	4
valid_sources[0x1a]	400542	1			T3	3		T5	2		T6	8
valid_sources[0x1b]	386648	1			T1	10		T3	9		T5	4
valid_sources[0x1c]	401520	1			T1	31		T3	2		T5	5
valid_sources[0x1d]	401519	1			T1	20		T3	8		T5	7
valid_sources[0x1e]	442316	1			T1	9		T3	5		T5	2
valid_sources[0x1f]	383891	1			T1	42		T3	7		T5	6
valid_sources[0x20]	426494	1			T3	5		T5	7		T6	7
valid_sources[0x21]	395901	1			T1	5		T2	265		T3	5
valid_sources[0x22]	386730	1			T1	9		T3	6		T5	6
valid_sources[0x23]	376799	1			T1	23		T5	3		T6	9
valid_sources[0x24]	379095	1			T1	13		T3	3		T5	5
valid_sources[0x25]	425904	1			T3	1		T5	3		T6	5
valid_sources[0x26]	392912	1			T1	21		T3	5		T5	3
valid_sources[0x27]	409722	1			T1	1		T3	4		T5	4
valid_sources[0x28]	391031	1			T3	5		T5	11		T6	7
valid_sources[0x29]	428038	1			T3	3		T6	1		T7	10
valid_sources[0x2a]	501737	1			T1	13		T3	9		T6	9
valid_sources[0x2b]	443918	1			T3	9		T5	4		T6	6
valid_sources[0x2c]	399626	1			T1	25		T3	2		T5	3
valid_sources[0x2d]	403822	1			T3	1		T5	3		T6	21
valid_sources[0x2e]	401015	1			T1	10		T3	2		T5	6
valid_sources[0x2f]	400545	1			T1	17		T3	4		T5	1
valid_sources[0x30]	415577	1			T3	4		T5	1		T6	9
valid_sources[0x31]	405713	1			T1	3		T3	4		T5	2
valid_sources[0x32]	401228	1			T1	55		T3	3		T5	3
valid_sources[0x33]	404827	1			T3	5		T5	13		T6	4
valid_sources[0x34]	402037	1			T1	2		T3	4		T5	2
valid_sources[0x35]	399156	1			T1	4		T3	5		T5	8
valid_sources[0x36]	409040	1			T1	4		T3	1		T5	1
valid_sources[0x37]	387911	1			T1	11		T3	7		T5	7
valid_sources[0x38]	408344	1			T1	7		T3	7		T5	9
valid_sources[0x39]	412539	1			T3	1		T5	7		T6	9
valid_sources[0x3a]	433761	1			T3	10		T5	3		T6	18
valid_sources[0x3b]	406135	1			T1	2		T3	4		T5	3
valid_sources[0x3c]	383409	1			T3	6		T5	3		T6	15
valid_sources[0x3d]	401078	1			T1	18		T3	5		T5	5
valid_sources[0x3e]	403040	1			T1	44		T3	6		T5	4
valid_sources[0x3f]	380488	1			T1	3		T5	2		T6	12
valid_sources[0x40]	428726	1			T3	2		T5	1		T6	8
valid_sources[0x41]	428095	1			T2	598		T3	1		T5	5
valid_sources[0x42]	388262	1			T1	10		T3	4		T5	10
valid_sources[0x43]	391698	1			T3	4		T5	4		T6	12
valid_sources[0x44]	392375	1			T1	8		T3	5		T5	4
valid_sources[0x45]	431664	1			T1	8		T3	4		T5	2
valid_sources[0x46]	407325	1			T1	23		T3	7		T5	5
valid_sources[0x47]	391678	1			T1	22		T3	5		T5	2
valid_sources[0x48]	392115	1			T1	16		T3	8		T5	3
valid_sources[0x49]	446520	1			T2	15561		T3	5		T5	4
valid_sources[0x4a]	386424	1			T1	6		T3	2		T6	13
valid_sources[0x4b]	375444	1			T1	24		T3	3		T5	5
valid_sources[0x4c]	381748	1			T1	19		T3	8		T5	3
valid_sources[0x4d]	452605	1			T3	5		T5	1		T6	8
valid_sources[0x4e]	394322	1			T1	17		T3	3		T5	4
valid_sources[0x4f]	387641	1			T1	4		T3	10		T5	1
valid_sources[0x50]	483746	1			T1	20		T5	1		T6	23
valid_sources[0x51]	399196	1			T1	7		T3	8		T6	8
valid_sources[0x52]	573145	1			T1	7		T3	5		T5	7
valid_sources[0x53]	400495	1			T3	9		T5	5		T6	13
valid_sources[0x54]	377044	1			T1	5		T3	7		T5	5
valid_sources[0x55]	438537	1			T3	3		T5	3		T6	15
valid_sources[0x56]	393172	1			T1	9		T3	3		T5	7
valid_sources[0x57]	415203	1			T1	40		T3	7		T5	3
valid_sources[0x58]	397043	1			T1	7		T3	3		T5	5
valid_sources[0x59]	424686	1			T1	3		T3	4		T5	3
valid_sources[0x5a]	386708	1			T1	30		T3	7		T5	6
valid_sources[0x5b]	549138	1			T3	5		T5	10		T6	11
valid_sources[0x5c]	406247	1			T1	18		T3	5		T5	3
valid_sources[0x5d]	412201	1			T1	9		T3	8		T5	5
valid_sources[0x5e]	481518	1			T1	4		T2	2775		T3	2
valid_sources[0x5f]	388915	1			T1	19		T3	3		T5	4
valid_sources[0x60]	400760	1			T3	7		T5	2		T6	11
valid_sources[0x61]	391924	1			T1	6		T3	10		T5	4
valid_sources[0x62]	418731	1			T1	5		T3	7		T5	3
valid_sources[0x63]	522003	1			T3	1		T5	11		T6	3
valid_sources[0x64]	392730	1			T1	9		T3	8		T5	6
valid_sources[0x65]	398839	1			T1	26		T3	4		T5	3
valid_sources[0x66]	402140	1			T3	3		T5	3		T6	7
valid_sources[0x67]	398223	1			T1	22		T3	5		T5	7
valid_sources[0x68]	393581	1			T1	3		T3	6		T5	5
valid_sources[0x69]	436839	1			T1	13		T3	2		T5	9
valid_sources[0x6a]	405218	1			T1	17		T3	10		T5	5
valid_sources[0x6b]	450649	1			T1	4		T3	5		T5	4
valid_sources[0x6c]	396617	1			T3	3		T5	1		T6	23
valid_sources[0x6d]	406319	1			T1	2		T3	4		T5	1
valid_sources[0x6e]	394124	1			T1	3		T3	3		T5	5
valid_sources[0x6f]	386190	1			T1	15		T3	1		T5	6
valid_sources[0x70]	403541	1			T3	8		T5	3		T6	5
valid_sources[0x71]	394661	1			T1	40		T3	6		T5	7
valid_sources[0x72]	431651	1			T1	1		T3	5		T5	1
valid_sources[0x73]	419572	1			T1	5		T3	4		T5	3
valid_sources[0x74]	425973	1			T1	12		T3	1		T5	11
valid_sources[0x75]	515613	1			T1	8		T3	3		T5	4
valid_sources[0x76]	379046	1			T1	18		T2	17		T3	9
valid_sources[0x77]	401262	1			T3	4		T5	1		T6	4
valid_sources[0x78]	382697	1			T3	14		T5	2		T6	3
valid_sources[0x79]	401650	1			T3	7		T5	6		T6	7
valid_sources[0x7a]	429899	1			T1	28		T3	3		T5	6
valid_sources[0x7b]	389904	1			T1	19		T3	5		T5	5
valid_sources[0x7c]	389488	1			T1	2		T3	3		T5	6
valid_sources[0x7d]	411185	1			T3	3		T5	4		T6	5
valid_sources[0x7e]	383065	1			T1	15		T3	3		T6	7
valid_sources[0x7f]	409512	1			T1	2		T3	4		T5	10
valid_sources[0x80]	384291	1			T1	2		T3	9		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20185705

1

T1

7

T2

65

T3

47

values[0x0]

all_enables

biggest_size

4638379

1

T1

3

T2

52

T3

30

values[0x1]

all_enables

biggest_size

4578694

1

T1

3

T2

26

T3

22