Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15090087	0	0
ctrl_rd_A	2147483647	377694	0	0
intr_enable_rd_A	2147483647	330864	0	0
ovrd_rd_A	2147483647	376882	0	0
timeout_ctrl_rd_A	2147483647	375452	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15090087	0	0
T11	126364	288095	0	0
T12	0	108905	0	0
T13	603162	182779	0	0
T15	40352	0	0	0
T30	0	223571	0	0
T31	0	66657	0	0
T32	0	66736	0	0
T33	0	60016	0	0
T34	0	113592	0	0
T35	0	142133	0	0
T36	0	171540	0	0
T37	133811	0	0	0
T38	284776	0	0	0
T39	183930	0	0	0
T40	622655	0	0	0
T41	932251	0	0	0
T42	401563	0	0	0
T43	428748	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	377694	0	0
T11	126364	12694	0	0
T13	603162	0	0	0
T15	40352	0	0	0
T31	0	3687	0	0
T32	0	7474	0	0
T37	133811	0	0	0
T38	284776	0	0	0
T39	183930	0	0	0
T40	622655	0	0	0
T41	932251	0	0	0
T42	401563	0	0	0
T43	428748	0	0	0
T59	0	15588	0	0
T111	0	13216	0	0
T112	0	28748	0	0
T113	0	2729	0	0
T114	0	6198	0	0
T115	0	6506	0	0
T116	0	8162	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	330864	0	0
T11	126364	10641	0	0
T13	603162	0	0	0
T15	40352	0	0	0
T31	0	3124	0	0
T32	0	6784	0	0
T37	133811	0	0	0
T38	284776	0	0	0
T39	183930	0	0	0
T40	622655	0	0	0
T41	932251	0	0	0
T42	401563	0	0	0
T43	428748	0	0	0
T59	0	13077	0	0
T111	0	11301	0	0
T112	0	24777	0	0
T113	0	2440	0	0
T114	0	5613	0	0
T115	0	6039	0	0
T116	0	7336	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	376882	0	0
T11	126364	13102	0	0
T13	603162	0	0	0
T15	40352	0	0	0
T31	0	3772	0	0
T32	0	7192	0	0
T37	133811	0	0	0
T38	284776	0	0	0
T39	183930	0	0	0
T40	622655	0	0	0
T41	932251	0	0	0
T42	401563	0	0	0
T43	428748	0	0	0
T59	0	15412	0	0
T111	0	13169	0	0
T112	0	29210	0	0
T113	0	2843	0	0
T114	0	6180	0	0
T115	0	6713	0	0
T116	0	8036	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	375452	0	0
T11	126364	12335	0	0
T13	603162	0	0	0
T15	40352	0	0	0
T31	0	3903	0	0
T32	0	7313	0	0
T37	133811	0	0	0
T38	284776	0	0	0
T39	183930	0	0	0
T40	622655	0	0	0
T41	932251	0	0	0
T42	401563	0	0	0
T43	428748	0	0	0
T59	0	15357	0	0
T111	0	13039	0	0
T112	0	29077	0	0
T113	0	3127	0	0
T114	0	6137	0	0
T115	0	6883	0	0
T116	0	7949	0	0