Module Definition
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Module : uart_tx
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.uart_core.uart_tx 100.00 100.00 100.00 100.00



Module Instance : tb.dut.uart_core.uart_tx

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.98 98.92 99.02 97.96 100.00 uart_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : uart_tx
Line No.TotalCoveredPercent
TOTAL2929100.00
CONT_ASSIGN3211100.00
ALWAYS3566100.00
ALWAYS4677100.00
ALWAYS581414100.00
CONT_ASSIGN7711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
41 1 1
46 1 1
47 1 1
48 1 1
49 1 1
51 1 1
52 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 1 1
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
77 1 1


Cond Coverage for Module : uart_tx
TotalCoveredPercent
Conditions1313100.00
Logical1313100.00
Non-Logical00
Event00

 LINE       67
 SUB-EXPRESSION (parity_enable ? wr_parity : 1'b1)
                 ------1------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (parity_enable ? 4'd11 : 4'd10)
             ------1------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       69
 EXPRESSION (tick_baud_q && (bit_cnt_q != 4'b0))
             -----1-----    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       69
 SUB-EXPRESSION (bit_cnt_q != 4'b0)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       77
 EXPRESSION (tx_enable ? (bit_cnt_q == 4'b0) : 1'b1)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       77
 SUB-EXPRESSION (bit_cnt_q == 4'b0)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : uart_tx
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 77 2 2 100.00
IF 35 3 3 100.00
IF 46 2 2 100.00
IF 58 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 77 (tx_enable) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 35 if ((!rst_ni)) -2-: 38 if (tick_baud_x16)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 46 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 58 if ((!tx_enable)) -2-: 66 if (wr) -3-: 68 (parity_enable) ? -4-: 69 if ((tick_baud_q && (bit_cnt_q != 4'b0)))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 1 - Covered T1,T2,T3
0 1 0 - Covered T1,T2,T5
0 0 - 1 Covered T1,T2,T3
0 0 - 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%