Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74230328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29378528

1

T1

154

T2

64980

T3

120

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	93758813	1			T1	159363		T2	22334		T3	34893
values[0x0]	4652915	1			T1	167		T2	24715		T3	109
values[0x1]	5197128	1			T1	156		T2	27662		T3	130

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51525249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52083607

1

T1

53268

T2

69324

T3

11675

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	392734	1			T2	655		T5	65		T9	41
valid_sources[0x01]	452707	1			T2	250		T5	56		T9	23
valid_sources[0x02]	422449	1			T2	711		T5	61		T8	4
valid_sources[0x03]	428098	1			T2	150		T5	57		T10	1207
valid_sources[0x04]	409491	1			T2	104		T5	63		T8	2
valid_sources[0x05]	361309	1			T2	477		T5	56		T9	4
valid_sources[0x06]	393175	1			T2	472		T5	41		T8	2
valid_sources[0x07]	391151	1			T2	705		T5	41		T8	1
valid_sources[0x08]	392101	1			T2	156		T5	53		T8	3
valid_sources[0x09]	392543	1			T1	2		T2	648		T5	49
valid_sources[0x0a]	393071	1			T1	26		T2	850		T5	47
valid_sources[0x0b]	390396	1			T2	523		T5	66		T9	18
valid_sources[0x0c]	418310	1			T2	244		T4	16		T5	74
valid_sources[0x0d]	382714	1			T2	291		T5	40		T9	2
valid_sources[0x0e]	389287	1			T1	1398		T2	526		T5	53
valid_sources[0x0f]	505230	1			T1	21498		T2	284		T5	64
valid_sources[0x10]	390162	1			T2	377		T5	61		T9	15
valid_sources[0x11]	386391	1			T2	237		T5	65		T9	6
valid_sources[0x12]	382698	1			T2	76		T5	49		T10	1130
valid_sources[0x13]	423851	1			T2	306		T5	54		T10	1118
valid_sources[0x14]	411853	1			T2	420		T5	53		T9	40
valid_sources[0x15]	370591	1			T2	213		T5	46		T8	3
valid_sources[0x16]	398924	1			T2	373		T5	54		T10	1119
valid_sources[0x17]	367038	1			T2	239		T5	53		T8	1
valid_sources[0x18]	399500	1			T2	268		T5	61		T8	1
valid_sources[0x19]	418949	1			T2	414		T5	65		T9	59
valid_sources[0x1a]	376351	1			T2	481		T5	64		T8	1
valid_sources[0x1b]	386833	1			T2	234		T5	57		T10	1122
valid_sources[0x1c]	376124	1			T2	386		T5	59		T10	1125
valid_sources[0x1d]	376446	1			T2	81		T5	69		T9	3
valid_sources[0x1e]	406748	1			T2	287		T5	47		T9	4
valid_sources[0x1f]	547799	1			T2	161		T5	47		T9	4
valid_sources[0x20]	398951	1			T2	80		T5	43		T8	1
valid_sources[0x21]	382082	1			T2	433		T5	54		T9	21
valid_sources[0x22]	397464	1			T2	252		T5	60		T9	21
valid_sources[0x23]	392453	1			T2	126		T5	59		T9	23
valid_sources[0x24]	400887	1			T2	460		T5	61		T9	22
valid_sources[0x25]	384443	1			T1	1824		T2	11		T5	51
valid_sources[0x26]	399701	1			T2	759		T5	65		T10	1084
valid_sources[0x27]	398238	1			T2	677		T5	57		T9	31
valid_sources[0x28]	462362	1			T1	1		T2	20		T5	48
valid_sources[0x29]	433575	1			T2	28		T5	47		T8	2
valid_sources[0x2a]	406033	1			T2	321		T5	47		T10	1105
valid_sources[0x2b]	398197	1			T2	59		T5	66		T8	1
valid_sources[0x2c]	395102	1			T1	1504		T2	255		T5	54
valid_sources[0x2d]	400414	1			T2	189		T5	58		T9	11
valid_sources[0x2e]	379227	1			T2	437		T5	53		T10	1141
valid_sources[0x2f]	379508	1			T2	132		T5	59		T9	7
valid_sources[0x30]	394903	1			T1	34		T2	19		T5	53
valid_sources[0x31]	419942	1			T1	1311		T2	74		T4	3
valid_sources[0x32]	410227	1			T2	135		T5	60		T9	3
valid_sources[0x33]	406990	1			T2	337		T5	55		T8	2
valid_sources[0x34]	391085	1			T2	306		T5	50		T9	7
valid_sources[0x35]	410448	1			T2	302		T5	55		T9	9
valid_sources[0x36]	405097	1			T2	180		T5	47		T8	2
valid_sources[0x37]	397811	1			T2	17		T4	4		T5	62
valid_sources[0x38]	388618	1			T2	17		T5	53		T9	10
valid_sources[0x39]	383107	1			T2	276		T5	58		T9	45
valid_sources[0x3a]	390575	1			T2	454		T5	50		T8	1
valid_sources[0x3b]	371983	1			T2	543		T5	48		T9	15
valid_sources[0x3c]	394446	1			T2	180		T5	55		T8	1
valid_sources[0x3d]	452181	1			T2	200		T5	44		T8	1
valid_sources[0x3e]	428959	1			T2	496		T5	41		T6	1673
valid_sources[0x3f]	398142	1			T2	331		T5	52		T9	3
valid_sources[0x40]	390845	1			T2	48		T5	56		T8	1
valid_sources[0x41]	379562	1			T2	239		T5	56		T10	1109
valid_sources[0x42]	495854	1			T1	1242		T2	349		T5	49
valid_sources[0x43]	401430	1			T2	279		T5	56		T9	8
valid_sources[0x44]	377288	1			T2	46		T5	70		T10	1063
valid_sources[0x45]	396601	1			T1	172		T2	267		T5	44
valid_sources[0x46]	382856	1			T1	1		T2	189		T5	60
valid_sources[0x47]	483698	1			T2	119		T5	52		T9	16
valid_sources[0x48]	375792	1			T1	1		T2	118		T5	62
valid_sources[0x49]	416567	1			T2	308		T5	52		T8	1
valid_sources[0x4a]	415209	1			T2	422		T5	52		T9	28
valid_sources[0x4b]	400251	1			T1	3152		T2	322		T5	52
valid_sources[0x4c]	391873	1			T2	589		T4	4		T5	56
valid_sources[0x4d]	401307	1			T2	214		T5	50		T8	1
valid_sources[0x4e]	384385	1			T2	153		T4	12		T5	64
valid_sources[0x4f]	390727	1			T2	342		T5	50		T8	1
valid_sources[0x50]	388364	1			T2	81		T4	166		T5	56
valid_sources[0x51]	410299	1			T2	296		T5	61		T8	3
valid_sources[0x52]	414139	1			T2	89		T5	53		T9	33
valid_sources[0x53]	398761	1			T2	514		T5	52		T8	1
valid_sources[0x54]	391927	1			T2	327		T5	41		T8	1
valid_sources[0x55]	386279	1			T2	228		T5	43		T10	1135
valid_sources[0x56]	381737	1			T2	417		T5	43		T9	9
valid_sources[0x57]	385259	1			T2	425		T5	48		T9	7
valid_sources[0x58]	393767	1			T1	7		T2	14		T5	62
valid_sources[0x59]	403784	1			T2	96		T5	44		T8	1
valid_sources[0x5a]	472815	1			T2	571		T4	11		T5	56
valid_sources[0x5b]	400400	1			T2	564		T5	48		T9	4
valid_sources[0x5c]	427569	1			T2	189		T5	56		T8	1
valid_sources[0x5d]	403776	1			T2	85		T5	54		T10	1127
valid_sources[0x5e]	376179	1			T2	15		T5	60		T10	1117
valid_sources[0x5f]	385308	1			T2	23		T5	50		T9	4
valid_sources[0x60]	416101	1			T2	448		T5	59		T8	1
valid_sources[0x61]	415616	1			T2	525		T5	53		T9	25
valid_sources[0x62]	486796	1			T2	319		T5	46		T9	16
valid_sources[0x63]	397780	1			T2	324		T5	66		T9	20
valid_sources[0x64]	403369	1			T1	2584		T2	84		T5	70
valid_sources[0x65]	384961	1			T2	523		T5	64		T8	2
valid_sources[0x66]	449936	1			T2	344		T5	47		T10	1147
valid_sources[0x67]	398073	1			T2	646		T5	60		T9	10
valid_sources[0x68]	395099	1			T2	404		T5	63		T10	1112
valid_sources[0x69]	428515	1			T1	28182		T2	152		T5	55
valid_sources[0x6a]	460983	1			T2	223		T4	46		T5	58
valid_sources[0x6b]	410498	1			T2	235		T5	63		T9	29
valid_sources[0x6c]	410225	1			T2	442		T5	58		T9	19
valid_sources[0x6d]	399846	1			T2	127		T5	58		T8	2
valid_sources[0x6e]	393203	1			T2	341		T4	63		T5	57
valid_sources[0x6f]	396688	1			T2	209		T5	48		T8	2
valid_sources[0x70]	381744	1			T2	226		T4	89		T5	54
valid_sources[0x71]	476208	1			T2	346		T5	44		T8	1
valid_sources[0x72]	386015	1			T2	122		T5	35		T10	1086
valid_sources[0x73]	401785	1			T2	837		T5	51		T9	27
valid_sources[0x74]	376287	1			T2	50		T5	55		T8	1
valid_sources[0x75]	408245	1			T2	328		T5	50		T8	1
valid_sources[0x76]	384413	1			T1	18		T2	518		T5	52
valid_sources[0x77]	416266	1			T2	134		T5	57		T9	3
valid_sources[0x78]	402253	1			T2	308		T5	46		T9	7
valid_sources[0x79]	378252	1			T2	214		T4	28		T5	69
valid_sources[0x7a]	391677	1			T2	191		T5	45		T10	1222
valid_sources[0x7b]	401461	1			T2	94		T5	50		T9	3
valid_sources[0x7c]	385748	1			T2	815		T5	65		T9	6
valid_sources[0x7d]	394426	1			T2	441		T5	58		T8	1
valid_sources[0x7e]	429965	1			T2	4		T5	42		T8	2
valid_sources[0x7f]	398968	1			T2	480		T5	44		T9	17
valid_sources[0x80]	400806	1			T2	438		T5	45		T9	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20648896

1

T1

49

T2

16446

T3

45

values[0x0]

all_enables

biggest_size

4394682

1

T1

69

T2

24363

T3

41

values[0x1]

all_enables

biggest_size

4334950

1

T1

36

T2

24171

T3

34