Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14636662	0	0
ctrl_rd_A	2147483647	154686	0	0
intr_enable_rd_A	2147483647	136798	0	0
ovrd_rd_A	2147483647	153325	0	0
timeout_ctrl_rd_A	2147483647	153315	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14636662	0	0
T2	425321	82416	0	0
T3	143732	0	0	0
T4	140949	0	0	0
T5	171051	0	0	0
T6	124092	0	0	0
T7	258111	0	0	0
T8	906591	0	0	0
T9	206664	0	0	0
T10	331900	75970	0	0
T11	255279	0	0	0
T13	0	88139	0	0
T22	0	257059	0	0
T29	0	227823	0	0
T30	0	212246	0	0
T31	0	135022	0	0
T32	0	102597	0	0
T33	0	162488	0	0
T34	0	87407	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	154686	0	0
T12	917472	0	0	0
T13	381360	2757	0	0
T16	85660	0	0	0
T21	122530	0	0	0
T31	0	14840	0	0
T32	0	9079	0	0
T35	207435	0	0	0
T36	32909	0	0	0
T40	858339	0	0	0
T41	987112	0	0	0
T42	861197	0	0	0
T43	636316	0	0	0
T92	0	4118	0	0
T93	0	3812	0	0
T94	0	8985	0	0
T95	0	7169	0	0
T96	0	8954	0	0
T97	0	9713	0	0
T98	0	8111	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	136798	0	0
T12	917472	0	0	0
T13	381360	2259	0	0
T16	85660	0	0	0
T21	122530	0	0	0
T31	0	13468	0	0
T32	0	8406	0	0
T35	207435	0	0	0
T36	32909	0	0	0
T40	858339	0	0	0
T41	987112	0	0	0
T42	861197	0	0	0
T43	636316	0	0	0
T92	0	3807	0	0
T93	0	3264	0	0
T94	0	7924	0	0
T95	0	6337	0	0
T96	0	8094	0	0
T97	0	8305	0	0
T98	0	7263	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	153325	0	0
T12	917472	0	0	0
T13	381360	2602	0	0
T16	85660	0	0	0
T21	122530	0	0	0
T31	0	15213	0	0
T32	0	9548	0	0
T35	207435	0	0	0
T36	32909	0	0	0
T40	858339	0	0	0
T41	987112	0	0	0
T42	861197	0	0	0
T43	636316	0	0	0
T92	0	4020	0	0
T93	0	3857	0	0
T94	0	8893	0	0
T95	0	7069	0	0
T96	0	9097	0	0
T97	0	9318	0	0
T98	0	7962	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	153315	0	0
T12	917472	0	0	0
T13	381360	2728	0	0
T16	85660	0	0	0
T21	122530	0	0	0
T31	0	14844	0	0
T32	0	9166	0	0
T35	207435	0	0	0
T36	32909	0	0	0
T40	858339	0	0	0
T41	987112	0	0	0
T42	861197	0	0	0
T43	636316	0	0	0
T92	0	4104	0	0
T93	0	3886	0	0
T94	0	9247	0	0
T95	0	6998	0	0
T96	0	9329	0	0
T97	0	9637	0	0
T98	0	7824	0	0