Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	75474713	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29010329

1

T1

66

T2

125

T3

123

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	93597953	1			T1	4633		T2	112		T3	41719
values[0x0]	5148219	1			T1	74		T2	104		T3	156
values[0x1]	5738870	1			T1	83		T2	97		T3	167

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52130118	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52354924

1

T1

1578

T2

154

T3

13953

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	396899	1			T1	11		T3	156		T4	10
valid_sources[0x01]	388627	1			T1	28		T3	145		T4	6
valid_sources[0x02]	412818	1			T1	23		T3	172		T4	11
valid_sources[0x03]	379021	1			T1	2		T3	136		T4	15
valid_sources[0x04]	388614	1			T1	10		T3	124		T4	18
valid_sources[0x05]	451299	1			T1	8		T3	126		T4	18
valid_sources[0x06]	397251	1			T1	17		T3	188		T4	3
valid_sources[0x07]	402069	1			T1	15		T3	110		T4	14
valid_sources[0x08]	381169	1			T1	14		T3	117		T4	12
valid_sources[0x09]	386533	1			T1	24		T3	204		T4	9
valid_sources[0x0a]	421336	1			T1	22		T3	188		T4	8
valid_sources[0x0b]	378889	1			T1	11		T3	134		T4	20
valid_sources[0x0c]	374455	1			T1	27		T3	136		T4	22
valid_sources[0x0d]	380318	1			T1	13		T3	223		T4	3
valid_sources[0x0e]	394213	1			T1	5		T3	175		T4	10
valid_sources[0x0f]	421465	1			T1	15		T3	124		T4	10
valid_sources[0x10]	429220	1			T1	12		T2	4		T3	188
valid_sources[0x11]	380490	1			T1	29		T3	218		T4	20
valid_sources[0x12]	542373	1			T1	12		T3	140		T4	14
valid_sources[0x13]	399870	1			T1	16		T3	218		T4	11
valid_sources[0x14]	373231	1			T1	15		T3	209		T4	23
valid_sources[0x15]	399601	1			T1	7		T3	168		T4	10
valid_sources[0x16]	400322	1			T1	28		T3	162		T4	9
valid_sources[0x17]	421984	1			T1	24		T3	205		T4	8
valid_sources[0x18]	437297	1			T1	14		T3	207		T4	11
valid_sources[0x19]	395588	1			T1	11		T2	7		T3	224
valid_sources[0x1a]	438823	1			T1	8		T3	221		T4	5
valid_sources[0x1b]	456758	1			T1	21		T3	148		T4	10
valid_sources[0x1c]	387644	1			T1	18		T3	184		T4	5
valid_sources[0x1d]	375362	1			T1	14		T3	155		T4	8
valid_sources[0x1e]	402585	1			T1	14		T3	185		T4	6
valid_sources[0x1f]	386188	1			T1	30		T3	141		T4	15
valid_sources[0x20]	423184	1			T1	19		T3	144		T4	1
valid_sources[0x21]	388581	1			T1	27		T3	201		T4	12
valid_sources[0x22]	376126	1			T1	24		T2	4		T3	174
valid_sources[0x23]	383768	1			T1	19		T3	185		T4	9
valid_sources[0x24]	382538	1			T1	18		T3	94		T4	8
valid_sources[0x25]	382639	1			T1	18		T3	164		T4	16
valid_sources[0x26]	374040	1			T1	22		T3	199		T4	8
valid_sources[0x27]	413407	1			T1	20		T3	160		T4	8
valid_sources[0x28]	432737	1			T1	14		T3	164		T4	9
valid_sources[0x29]	392848	1			T1	13		T3	173		T4	1
valid_sources[0x2a]	379706	1			T1	17		T2	3		T3	196
valid_sources[0x2b]	433157	1			T1	29		T3	155		T4	8
valid_sources[0x2c]	397443	1			T1	15		T3	166		T4	7
valid_sources[0x2d]	386768	1			T1	24		T3	151		T4	9
valid_sources[0x2e]	381813	1			T1	8		T3	141		T4	23
valid_sources[0x2f]	402253	1			T1	20		T3	154		T4	7
valid_sources[0x30]	410284	1			T1	14		T3	103		T4	2
valid_sources[0x31]	383759	1			T1	14		T3	164		T4	19
valid_sources[0x32]	377828	1			T1	24		T3	177		T4	18
valid_sources[0x33]	425031	1			T1	20		T3	186		T4	1
valid_sources[0x34]	402188	1			T1	36		T2	10		T3	195
valid_sources[0x35]	381419	1			T1	24		T2	5		T3	180
valid_sources[0x36]	424572	1			T1	19		T3	119		T4	18
valid_sources[0x37]	446187	1			T1	26		T3	169		T4	7
valid_sources[0x38]	526906	1			T1	17		T3	132		T4	16
valid_sources[0x39]	388758	1			T1	12		T3	174		T4	13
valid_sources[0x3a]	386270	1			T1	21		T3	254		T4	10
valid_sources[0x3b]	395076	1			T1	22		T3	167		T4	7
valid_sources[0x3c]	391710	1			T1	22		T3	131		T4	6
valid_sources[0x3d]	459047	1			T1	13		T2	4		T3	150
valid_sources[0x3e]	416835	1			T1	32		T3	178		T4	7
valid_sources[0x3f]	372650	1			T1	14		T3	171		T4	4
valid_sources[0x40]	404551	1			T1	26		T3	125		T4	14
valid_sources[0x41]	414846	1			T1	10		T3	175		T4	12
valid_sources[0x42]	457055	1			T1	25		T3	148		T4	14
valid_sources[0x43]	388008	1			T1	7		T3	193		T4	18
valid_sources[0x44]	392897	1			T1	39		T3	110		T4	21
valid_sources[0x45]	386402	1			T1	19		T3	187		T4	10
valid_sources[0x46]	403518	1			T1	12		T3	125		T4	10
valid_sources[0x47]	430075	1			T1	4		T3	159		T4	12
valid_sources[0x48]	385897	1			T1	21		T3	183		T4	23
valid_sources[0x49]	373795	1			T1	12		T3	165		T4	8
valid_sources[0x4a]	385051	1			T1	13		T3	178		T4	8
valid_sources[0x4b]	388360	1			T1	19		T3	128		T4	18
valid_sources[0x4c]	411228	1			T1	12		T3	176		T4	4
valid_sources[0x4d]	389263	1			T1	10		T3	190		T4	10
valid_sources[0x4e]	372314	1			T1	24		T3	228		T4	8
valid_sources[0x4f]	475054	1			T1	20		T3	237		T4	9
valid_sources[0x50]	408237	1			T1	27		T3	160		T4	4
valid_sources[0x51]	446153	1			T1	21		T3	157		T4	11
valid_sources[0x52]	375337	1			T1	9		T3	136		T4	12
valid_sources[0x53]	408019	1			T1	35		T3	182		T4	12
valid_sources[0x54]	398044	1			T1	19		T3	182		T4	9
valid_sources[0x55]	592470	1			T1	12		T3	220		T4	16
valid_sources[0x56]	388859	1			T1	3		T2	13		T3	136
valid_sources[0x57]	409197	1			T1	20		T2	9		T3	145
valid_sources[0x58]	436490	1			T1	21		T3	135		T4	12
valid_sources[0x59]	447644	1			T1	13		T2	12		T3	203
valid_sources[0x5a]	507092	1			T1	14		T3	172		T4	10
valid_sources[0x5b]	379897	1			T1	17		T2	4		T3	170
valid_sources[0x5c]	608479	1			T1	17		T2	1		T3	185
valid_sources[0x5d]	425629	1			T1	19		T3	170		T4	8
valid_sources[0x5e]	377283	1			T1	40		T3	150		T4	5
valid_sources[0x5f]	392927	1			T1	14		T3	179		T4	7
valid_sources[0x60]	388504	1			T1	41		T2	13		T3	185
valid_sources[0x61]	411730	1			T1	13		T3	216		T4	3
valid_sources[0x62]	406561	1			T1	6		T3	175		T4	8
valid_sources[0x63]	470375	1			T1	28		T3	204		T4	14
valid_sources[0x64]	402532	1			T1	11		T3	172		T4	7
valid_sources[0x65]	379598	1			T1	19		T3	145		T4	13
valid_sources[0x66]	383324	1			T1	31		T3	150		T4	16
valid_sources[0x67]	434343	1			T1	13		T2	2		T3	176
valid_sources[0x68]	377425	1			T1	15		T2	5		T3	141
valid_sources[0x69]	396773	1			T1	29		T3	136		T4	6
valid_sources[0x6a]	389299	1			T1	11		T3	222		T4	11
valid_sources[0x6b]	373406	1			T1	7		T3	121		T4	16
valid_sources[0x6c]	383859	1			T1	15		T3	195		T4	13
valid_sources[0x6d]	391699	1			T1	15		T3	170		T4	5
valid_sources[0x6e]	396598	1			T1	24		T3	147		T4	2
valid_sources[0x6f]	397810	1			T1	14		T2	5		T3	160
valid_sources[0x70]	633777	1			T1	24		T3	165		T4	4
valid_sources[0x71]	385365	1			T1	18		T3	158		T4	9
valid_sources[0x72]	419292	1			T1	24		T3	156		T4	6
valid_sources[0x73]	420300	1			T1	11		T3	195		T4	21
valid_sources[0x74]	506127	1			T1	27		T2	18		T3	172
valid_sources[0x75]	404355	1			T1	16		T3	125		T4	25
valid_sources[0x76]	408851	1			T1	10		T3	196		T5	1743
valid_sources[0x77]	381109	1			T1	17		T2	14		T3	201
valid_sources[0x78]	394421	1			T1	16		T2	3		T3	152
valid_sources[0x79]	382330	1			T1	26		T2	1		T3	165
valid_sources[0x7a]	396764	1			T1	25		T3	238		T4	7
valid_sources[0x7b]	425953	1			T1	20		T3	91		T4	14
valid_sources[0x7c]	388906	1			T1	34		T3	154		T4	1
valid_sources[0x7d]	380073	1			T1	19		T3	204		T4	15
valid_sources[0x7e]	429476	1			T1	23		T3	170		T4	14
valid_sources[0x7f]	387171	1			T1	18		T3	175		T4	18
valid_sources[0x80]	375662	1			T1	31		T2	32		T3	165

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19334294

1

T1

30

T2

60

T3

34

values[0x0]

all_enables

biggest_size

4869159

1

T1

17

T2

37

T3

52

values[0x1]

all_enables

biggest_size

4806876

1

T1

19

T2

28

T3

37