Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15913920	0	0
ctrl_rd_A	2147483647	353567	0	0
intr_enable_rd_A	2147483647	314278	0	0
ovrd_rd_A	2147483647	350111	0	0
timeout_ctrl_rd_A	2147483647	354260	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15913920	0	0
T5	242281	92621	0	0
T6	149545	0	0	0
T7	204419	0	0	0
T8	253797	0	0	0
T9	202515	0	0	0
T10	110895	0	0	0
T11	123907	0	0	0
T12	174562	0	0	0
T13	0	111659	0	0
T15	0	332558	0	0
T17	0	194066	0	0
T18	0	134472	0	0
T23	0	125016	0	0
T31	117612	0	0	0
T33	0	213000	0	0
T34	0	111581	0	0
T35	0	217913	0	0
T36	0	132821	0	0
T37	985657	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	353567	0	0
T13	467028	12414	0	0
T14	535532	0	0	0
T15	952757	0	0	0
T16	385719	0	0	0
T19	0	7232	0	0
T23	302372	0	0	0
T25	982	0	0	0
T34	0	4908	0	0
T35	0	23465	0	0
T49	0	4137	0	0
T50	0	18167	0	0
T106	0	10204	0	0
T107	0	6894	0	0
T108	0	3477	0	0
T109	0	30318	0	0
T110	103402	0	0	0
T111	442795	0	0	0
T112	197170	0	0	0
T113	64243	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	314278	0	0
T13	467028	11003	0	0
T14	535532	0	0	0
T15	952757	0	0	0
T16	385719	0	0	0
T19	0	6565	0	0
T23	302372	0	0	0
T25	982	0	0	0
T34	0	4452	0	0
T35	0	21293	0	0
T49	0	3521	0	0
T50	0	16405	0	0
T106	0	9326	0	0
T107	0	6173	0	0
T108	0	3116	0	0
T109	0	27297	0	0
T110	103402	0	0	0
T111	442795	0	0	0
T112	197170	0	0	0
T113	64243	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350111	0	0
T13	467028	12612	0	0
T14	535532	0	0	0
T15	952757	0	0	0
T16	385719	0	0	0
T19	0	7043	0	0
T23	302372	0	0	0
T25	982	0	0	0
T34	0	4748	0	0
T35	0	23221	0	0
T49	0	4229	0	0
T50	0	18281	0	0
T106	0	10596	0	0
T107	0	7430	0	0
T108	0	3694	0	0
T109	0	30509	0	0
T110	103402	0	0	0
T111	442795	0	0	0
T112	197170	0	0	0
T113	64243	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	354260	0	0
T13	467028	12843	0	0
T14	535532	0	0	0
T15	952757	0	0	0
T16	385719	0	0	0
T19	0	7391	0	0
T23	302372	0	0	0
T25	982	0	0	0
T34	0	5204	0	0
T35	0	23736	0	0
T49	0	4315	0	0
T50	0	18243	0	0
T106	0	10654	0	0
T107	0	7208	0	0
T108	0	3732	0	0
T109	0	30901	0	0
T110	103402	0	0	0
T111	442795	0	0	0
T112	197170	0	0	0
T113	64243	0	0	0