Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 83261069 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 29848263 1 T1 115 T2 221 T3 68



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 102911870 1 T1 525 T2 5128 T3 2609
values[0x0] 4819772 1 T1 48 T2 197 T3 86
values[0x1] 5377690 1 T1 34 T2 195 T3 85



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 57555070 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 55554262 1 T1 251 T2 1919 T3 928



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 412940 1 T1 1 T4 422 T5 343
valid_sources[0x01] 437755 1 T1 4 T4 252 T5 340
valid_sources[0x02] 463783 1 T1 2 T4 416 T5 331
valid_sources[0x03] 444951 1 T1 1 T4 311 T5 338
valid_sources[0x04] 418388 1 T1 2 T4 388 T5 393
valid_sources[0x05] 426799 1 T1 1 T4 464 T5 340
valid_sources[0x06] 426470 1 T1 2 T4 450 T5 341
valid_sources[0x07] 558778 1 T1 1 T4 341 T5 332
valid_sources[0x08] 433293 1 T1 2 T4 321 T5 318
valid_sources[0x09] 576966 1 T1 4 T4 401 T5 332
valid_sources[0x0a] 421929 1 T1 3 T4 418 T5 366
valid_sources[0x0b] 417033 1 T4 356 T5 352 T6 90
valid_sources[0x0c] 414058 1 T1 1 T4 436 T5 359
valid_sources[0x0d] 429890 1 T1 3 T4 326 T5 310
valid_sources[0x0e] 427440 1 T1 1 T4 299 T5 243
valid_sources[0x0f] 419359 1 T1 4 T4 406 T5 369
valid_sources[0x10] 414993 1 T1 2 T4 409 T5 369
valid_sources[0x11] 440106 1 T1 1 T4 435 T5 365
valid_sources[0x12] 503586 1 T4 395 T5 283 T6 101
valid_sources[0x13] 451348 1 T1 3 T4 269 T5 427
valid_sources[0x14] 447410 1 T1 4 T4 384 T5 363
valid_sources[0x15] 443066 1 T1 1 T4 317 T5 341
valid_sources[0x16] 458276 1 T1 4 T4 332 T5 341
valid_sources[0x17] 416887 1 T1 2 T4 480 T5 342
valid_sources[0x18] 524274 1 T1 1 T4 409 T5 295
valid_sources[0x19] 424367 1 T1 5 T4 448 T5 384
valid_sources[0x1a] 442692 1 T1 2 T4 390 T5 333
valid_sources[0x1b] 421444 1 T1 1 T4 426 T5 336
valid_sources[0x1c] 465418 1 T1 4 T4 425 T5 354
valid_sources[0x1d] 402400 1 T1 3 T4 366 T5 464
valid_sources[0x1e] 409618 1 T1 5 T4 417 T5 363
valid_sources[0x1f] 471191 1 T1 5 T4 416 T5 367
valid_sources[0x20] 419766 1 T1 4 T4 347 T5 390
valid_sources[0x21] 417046 1 T1 2 T4 434 T5 348
valid_sources[0x22] 399366 1 T1 5 T4 393 T5 289
valid_sources[0x23] 430361 1 T1 2 T4 263 T5 434
valid_sources[0x24] 440978 1 T1 1 T4 364 T5 360
valid_sources[0x25] 521238 1 T1 2 T4 284 T5 341
valid_sources[0x26] 411033 1 T1 2 T4 353 T5 284
valid_sources[0x27] 404104 1 T1 2 T4 392 T5 353
valid_sources[0x28] 414086 1 T1 5 T4 334 T5 384
valid_sources[0x29] 417474 1 T1 2 T4 432 T5 337
valid_sources[0x2a] 494389 1 T1 1 T4 368 T5 351
valid_sources[0x2b] 432774 1 T1 1 T4 395 T5 342
valid_sources[0x2c] 424861 1 T1 1 T4 333 T5 354
valid_sources[0x2d] 442868 1 T1 2 T4 308 T5 341
valid_sources[0x2e] 605345 1 T1 1 T4 412 T5 289
valid_sources[0x2f] 508661 1 T1 4 T4 419 T5 321
valid_sources[0x30] 443772 1 T1 2 T4 390 T5 270
valid_sources[0x31] 419880 1 T1 10 T4 435 T5 389
valid_sources[0x32] 425763 1 T1 3 T4 363 T5 282
valid_sources[0x33] 412608 1 T1 1 T4 409 T5 275
valid_sources[0x34] 437715 1 T1 1 T4 457 T5 321
valid_sources[0x35] 430726 1 T1 3 T4 388 T5 341
valid_sources[0x36] 431932 1 T1 1 T4 453 T5 325
valid_sources[0x37] 593714 1 T1 1 T4 407 T5 434
valid_sources[0x38] 422967 1 T1 4 T4 370 T5 334
valid_sources[0x39] 498941 1 T1 5 T4 549 T5 325
valid_sources[0x3a] 426332 1 T1 1 T3 1702 T4 345
valid_sources[0x3b] 432346 1 T1 3 T4 454 T5 337
valid_sources[0x3c] 454434 1 T4 350 T5 405 T6 102
valid_sources[0x3d] 431734 1 T1 2 T4 340 T5 384
valid_sources[0x3e] 526554 1 T1 3 T4 355 T5 336
valid_sources[0x3f] 422789 1 T1 1 T4 313 T5 340
valid_sources[0x40] 438049 1 T1 2 T4 421 T5 361
valid_sources[0x41] 413116 1 T1 2 T2 3010 T4 335
valid_sources[0x42] 450231 1 T1 1 T4 483 T5 324
valid_sources[0x43] 413801 1 T4 416 T5 340 T6 107
valid_sources[0x44] 417359 1 T4 359 T5 323 T6 105
valid_sources[0x45] 407466 1 T1 1 T4 336 T5 348
valid_sources[0x46] 403217 1 T1 5 T4 407 T5 308
valid_sources[0x47] 419678 1 T1 3 T4 239 T5 285
valid_sources[0x48] 403122 1 T1 2 T4 356 T5 334
valid_sources[0x49] 423791 1 T4 370 T5 327 T6 103
valid_sources[0x4a] 411842 1 T1 2 T4 267 T5 373
valid_sources[0x4b] 432969 1 T1 5 T4 444 T5 358
valid_sources[0x4c] 469188 1 T1 5 T4 246 T5 344
valid_sources[0x4d] 464992 1 T1 2 T4 305 T5 387
valid_sources[0x4e] 470612 1 T1 1 T4 315 T5 264
valid_sources[0x4f] 430377 1 T1 4 T4 424 T5 345
valid_sources[0x50] 425443 1 T1 4 T4 417 T5 302
valid_sources[0x51] 417507 1 T1 3 T4 410 T5 408
valid_sources[0x52] 450323 1 T1 1 T4 301 T5 268
valid_sources[0x53] 402230 1 T1 3 T4 406 T5 311
valid_sources[0x54] 496219 1 T1 1 T4 302 T5 323
valid_sources[0x55] 394879 1 T4 481 T5 341 T6 100
valid_sources[0x56] 426174 1 T1 1 T4 261 T5 317
valid_sources[0x57] 461932 1 T1 2 T4 320 T5 366
valid_sources[0x58] 435427 1 T4 389 T5 314 T6 92
valid_sources[0x59] 415073 1 T1 1 T4 393 T5 325
valid_sources[0x5a] 421161 1 T1 3 T4 296 T5 304
valid_sources[0x5b] 415056 1 T1 3 T4 442 T5 406
valid_sources[0x5c] 419151 1 T1 1 T4 320 T5 375
valid_sources[0x5d] 404057 1 T1 2 T4 355 T5 337
valid_sources[0x5e] 430066 1 T1 4 T4 347 T5 346
valid_sources[0x5f] 418833 1 T1 2 T2 1157 T4 429
valid_sources[0x60] 437955 1 T1 6 T4 455 T5 358
valid_sources[0x61] 442762 1 T1 3 T4 279 T5 390
valid_sources[0x62] 437218 1 T1 4 T4 314 T5 340
valid_sources[0x63] 403818 1 T1 2 T4 320 T5 345
valid_sources[0x64] 420505 1 T1 2 T4 437 T5 332
valid_sources[0x65] 429093 1 T1 7 T4 524 T5 309
valid_sources[0x66] 467614 1 T1 3 T2 1 T4 453
valid_sources[0x67] 422270 1 T1 3 T4 394 T5 373
valid_sources[0x68] 591579 1 T1 7 T4 503 T5 388
valid_sources[0x69] 463973 1 T1 4 T4 287 T5 373
valid_sources[0x6a] 424030 1 T4 325 T5 322 T6 88
valid_sources[0x6b] 428540 1 T1 1 T4 370 T5 309
valid_sources[0x6c] 419938 1 T4 456 T5 415 T6 110
valid_sources[0x6d] 423151 1 T1 5 T4 344 T5 324
valid_sources[0x6e] 444725 1 T1 4 T4 364 T5 312
valid_sources[0x6f] 426395 1 T1 1 T4 399 T5 294
valid_sources[0x70] 443725 1 T1 1 T4 464 T5 392
valid_sources[0x71] 424890 1 T2 1349 T4 368 T5 327
valid_sources[0x72] 556367 1 T1 3 T4 439 T5 308
valid_sources[0x73] 418001 1 T1 5 T4 377 T5 355
valid_sources[0x74] 424749 1 T1 7 T4 302 T5 361
valid_sources[0x75] 417723 1 T1 1 T4 398 T5 368
valid_sources[0x76] 529418 1 T1 1 T4 458 T5 383
valid_sources[0x77] 427120 1 T1 5 T4 403 T5 374
valid_sources[0x78] 435226 1 T1 3 T4 350 T5 376
valid_sources[0x79] 431486 1 T1 4 T4 327 T5 337
valid_sources[0x7a] 419702 1 T1 5 T4 326 T5 298
valid_sources[0x7b] 425618 1 T1 3 T4 341 T5 337
valid_sources[0x7c] 462318 1 T1 1 T4 420 T5 396
valid_sources[0x7d] 411293 1 T4 577 T5 391 T6 104
valid_sources[0x7e] 546860 1 T1 3 T4 474 T5 341
valid_sources[0x7f] 429511 1 T1 1 T4 509 T5 344
valid_sources[0x80] 574762 1 T1 1 T4 433 T5 335



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 20841756 1 T1 94 T2 86 T3 9
values[0x0] all_enables biggest_size 4535318 1 T1 12 T2 81 T3 39
values[0x1] all_enables biggest_size 4471189 1 T1 9 T2 54 T3 20

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%