Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1568548 |
600837 |
0 |
0 |
T2 |
299544 |
243200 |
0 |
0 |
T3 |
1048468 |
158272 |
0 |
0 |
T4 |
397550 |
159928 |
0 |
0 |
T5 |
617744 |
535126 |
0 |
0 |
T6 |
434682 |
163729 |
0 |
0 |
T7 |
1103290 |
549933 |
0 |
0 |
T8 |
456016 |
296767 |
0 |
0 |
T9 |
761546 |
431839 |
0 |
0 |
T10 |
1911980 |
542281 |
0 |
0 |
T11 |
0 |
97044 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1568548 |
1568398 |
0 |
0 |
T2 |
299544 |
299534 |
0 |
0 |
T3 |
1048468 |
1048356 |
0 |
0 |
T4 |
397550 |
397360 |
0 |
0 |
T5 |
617744 |
617730 |
0 |
0 |
T6 |
434682 |
434560 |
0 |
0 |
T7 |
1103290 |
1103186 |
0 |
0 |
T8 |
456016 |
456002 |
0 |
0 |
T9 |
761546 |
761536 |
0 |
0 |
T10 |
1911980 |
1911838 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1568548 |
1568398 |
0 |
0 |
T2 |
299544 |
299534 |
0 |
0 |
T3 |
1048468 |
1048356 |
0 |
0 |
T4 |
397550 |
397360 |
0 |
0 |
T5 |
617744 |
617730 |
0 |
0 |
T6 |
434682 |
434560 |
0 |
0 |
T7 |
1103290 |
1103186 |
0 |
0 |
T8 |
456016 |
456002 |
0 |
0 |
T9 |
761546 |
761536 |
0 |
0 |
T10 |
1911980 |
1911838 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1568548 |
1568398 |
0 |
0 |
T2 |
299544 |
299534 |
0 |
0 |
T3 |
1048468 |
1048356 |
0 |
0 |
T4 |
397550 |
397360 |
0 |
0 |
T5 |
617744 |
617730 |
0 |
0 |
T6 |
434682 |
434560 |
0 |
0 |
T7 |
1103290 |
1103186 |
0 |
0 |
T8 |
456016 |
456002 |
0 |
0 |
T9 |
761546 |
761536 |
0 |
0 |
T10 |
1911980 |
1911838 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1568548 |
600837 |
0 |
0 |
T2 |
299544 |
243200 |
0 |
0 |
T3 |
1048468 |
158272 |
0 |
0 |
T4 |
397550 |
159928 |
0 |
0 |
T5 |
617744 |
535126 |
0 |
0 |
T6 |
434682 |
163729 |
0 |
0 |
T7 |
1103290 |
549933 |
0 |
0 |
T8 |
456016 |
296767 |
0 |
0 |
T9 |
761546 |
431839 |
0 |
0 |
T10 |
1911980 |
542281 |
0 |
0 |
T11 |
0 |
97044 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2109775965 |
0 |
0 |
T1 |
784274 |
37728 |
0 |
0 |
T2 |
149772 |
132635 |
0 |
0 |
T3 |
524234 |
158272 |
0 |
0 |
T4 |
198775 |
158529 |
0 |
0 |
T5 |
308872 |
116709 |
0 |
0 |
T6 |
217341 |
0 |
0 |
0 |
T7 |
551645 |
401075 |
0 |
0 |
T8 |
228008 |
158209 |
0 |
0 |
T9 |
380773 |
408719 |
0 |
0 |
T10 |
955990 |
328079 |
0 |
0 |
T11 |
0 |
71889 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
784274 |
784199 |
0 |
0 |
T2 |
149772 |
149767 |
0 |
0 |
T3 |
524234 |
524178 |
0 |
0 |
T4 |
198775 |
198680 |
0 |
0 |
T5 |
308872 |
308865 |
0 |
0 |
T6 |
217341 |
217280 |
0 |
0 |
T7 |
551645 |
551593 |
0 |
0 |
T8 |
228008 |
228001 |
0 |
0 |
T9 |
380773 |
380768 |
0 |
0 |
T10 |
955990 |
955919 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
784274 |
784199 |
0 |
0 |
T2 |
149772 |
149767 |
0 |
0 |
T3 |
524234 |
524178 |
0 |
0 |
T4 |
198775 |
198680 |
0 |
0 |
T5 |
308872 |
308865 |
0 |
0 |
T6 |
217341 |
217280 |
0 |
0 |
T7 |
551645 |
551593 |
0 |
0 |
T8 |
228008 |
228001 |
0 |
0 |
T9 |
380773 |
380768 |
0 |
0 |
T10 |
955990 |
955919 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
784274 |
784199 |
0 |
0 |
T2 |
149772 |
149767 |
0 |
0 |
T3 |
524234 |
524178 |
0 |
0 |
T4 |
198775 |
198680 |
0 |
0 |
T5 |
308872 |
308865 |
0 |
0 |
T6 |
217341 |
217280 |
0 |
0 |
T7 |
551645 |
551593 |
0 |
0 |
T8 |
228008 |
228001 |
0 |
0 |
T9 |
380773 |
380768 |
0 |
0 |
T10 |
955990 |
955919 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2109775965 |
0 |
0 |
T1 |
784274 |
37728 |
0 |
0 |
T2 |
149772 |
132635 |
0 |
0 |
T3 |
524234 |
158272 |
0 |
0 |
T4 |
198775 |
158529 |
0 |
0 |
T5 |
308872 |
116709 |
0 |
0 |
T6 |
217341 |
0 |
0 |
0 |
T7 |
551645 |
401075 |
0 |
0 |
T8 |
228008 |
158209 |
0 |
0 |
T9 |
380773 |
408719 |
0 |
0 |
T10 |
955990 |
328079 |
0 |
0 |
T11 |
0 |
71889 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T10,T12 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T8,T10,T12 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
814356993 |
0 |
0 |
T1 |
784274 |
563109 |
0 |
0 |
T2 |
149772 |
110565 |
0 |
0 |
T3 |
524234 |
0 |
0 |
0 |
T4 |
198775 |
1399 |
0 |
0 |
T5 |
308872 |
418417 |
0 |
0 |
T6 |
217341 |
163729 |
0 |
0 |
T7 |
551645 |
148858 |
0 |
0 |
T8 |
228008 |
138558 |
0 |
0 |
T9 |
380773 |
23120 |
0 |
0 |
T10 |
955990 |
214202 |
0 |
0 |
T11 |
0 |
25155 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
784274 |
784199 |
0 |
0 |
T2 |
149772 |
149767 |
0 |
0 |
T3 |
524234 |
524178 |
0 |
0 |
T4 |
198775 |
198680 |
0 |
0 |
T5 |
308872 |
308865 |
0 |
0 |
T6 |
217341 |
217280 |
0 |
0 |
T7 |
551645 |
551593 |
0 |
0 |
T8 |
228008 |
228001 |
0 |
0 |
T9 |
380773 |
380768 |
0 |
0 |
T10 |
955990 |
955919 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
784274 |
784199 |
0 |
0 |
T2 |
149772 |
149767 |
0 |
0 |
T3 |
524234 |
524178 |
0 |
0 |
T4 |
198775 |
198680 |
0 |
0 |
T5 |
308872 |
308865 |
0 |
0 |
T6 |
217341 |
217280 |
0 |
0 |
T7 |
551645 |
551593 |
0 |
0 |
T8 |
228008 |
228001 |
0 |
0 |
T9 |
380773 |
380768 |
0 |
0 |
T10 |
955990 |
955919 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
784274 |
784199 |
0 |
0 |
T2 |
149772 |
149767 |
0 |
0 |
T3 |
524234 |
524178 |
0 |
0 |
T4 |
198775 |
198680 |
0 |
0 |
T5 |
308872 |
308865 |
0 |
0 |
T6 |
217341 |
217280 |
0 |
0 |
T7 |
551645 |
551593 |
0 |
0 |
T8 |
228008 |
228001 |
0 |
0 |
T9 |
380773 |
380768 |
0 |
0 |
T10 |
955990 |
955919 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
814356993 |
0 |
0 |
T1 |
784274 |
563109 |
0 |
0 |
T2 |
149772 |
110565 |
0 |
0 |
T3 |
524234 |
0 |
0 |
0 |
T4 |
198775 |
1399 |
0 |
0 |
T5 |
308872 |
418417 |
0 |
0 |
T6 |
217341 |
163729 |
0 |
0 |
T7 |
551645 |
148858 |
0 |
0 |
T8 |
228008 |
138558 |
0 |
0 |
T9 |
380773 |
23120 |
0 |
0 |
T10 |
955990 |
214202 |
0 |
0 |
T11 |
0 |
25155 |
0 |
0 |