Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14915739	0	0
ctrl_rd_A	2147483647	252487	0	0
intr_enable_rd_A	2147483647	225142	0	0
ovrd_rd_A	2147483647	253958	0	0
timeout_ctrl_rd_A	2147483647	252983	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14915739	0	0
T12	274800	0	0	0
T13	320615	85500	0	0
T14	559069	0	0	0
T15	575200	196675	0	0
T16	100934	421031	0	0
T27	0	60154	0	0
T28	0	222920	0	0
T29	0	123907	0	0
T30	0	121686	0	0
T31	0	229915	0	0
T32	0	76326	0	0
T33	0	289504	0	0
T34	933259	0	0	0
T35	413915	0	0	0
T36	632035	0	0	0
T37	159556	0	0	0
T38	319563	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	252487	0	0
T15	575200	5491	0	0
T20	192685	0	0	0
T27	163272	0	0	0
T33	0	31683	0	0
T38	319563	0	0	0
T39	128824	0	0	0
T40	116496	0	0	0
T41	163370	0	0	0
T42	556943	0	0	0
T58	0	12412	0	0
T110	0	755	0	0
T111	0	16470	0	0
T112	0	9534	0	0
T113	0	9571	0	0
T114	0	2390	0	0
T115	0	5973	0	0
T116	0	6310	0	0
T117	417328	0	0	0
T118	113364	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	225142	0	0
T15	575200	4856	0	0
T20	192685	0	0	0
T27	163272	0	0	0
T33	0	28401	0	0
T38	319563	0	0	0
T39	128824	0	0	0
T40	116496	0	0	0
T41	163370	0	0	0
T42	556943	0	0	0
T58	0	10865	0	0
T110	0	753	0	0
T111	0	14516	0	0
T112	0	8199	0	0
T113	0	8274	0	0
T114	0	2263	0	0
T115	0	5510	0	0
T117	417328	0	0	0
T118	113364	0	0	0
T119	0	16	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	253958	0	0
T15	575200	5631	0	0
T20	192685	0	0	0
T27	163272	0	0	0
T33	0	31226	0	0
T38	319563	0	0	0
T39	128824	0	0	0
T40	116496	0	0	0
T41	163370	0	0	0
T42	556943	0	0	0
T58	0	12386	0	0
T110	0	726	0	0
T111	0	16708	0	0
T112	0	9276	0	0
T113	0	9629	0	0
T114	0	2604	0	0
T115	0	5813	0	0
T116	0	6221	0	0
T117	417328	0	0	0
T118	113364	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	252983	0	0
T15	575200	5625	0	0
T20	192685	0	0	0
T27	163272	0	0	0
T33	0	32256	0	0
T38	319563	0	0	0
T39	128824	0	0	0
T40	116496	0	0	0
T41	163370	0	0	0
T42	556943	0	0	0
T58	0	12195	0	0
T110	0	779	0	0
T111	0	16055	0	0
T112	0	9487	0	0
T113	0	10147	0	0
T114	0	2554	0	0
T115	0	5872	0	0
T116	0	6545	0	0
T117	417328	0	0	0
T118	113364	0	0	0