Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	81555990	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31482997

1

T1

120

T2

183

T3

66989

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	102690271	1			T1	11557		T2	22375		T3	177518
values[0x0]	4894204	1			T1	157		T2	221		T3	330
values[0x1]	5454512	1			T1	141		T2	181		T3	306

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56574427	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

56464560

1

T1

4003

T2

7566

T3

94777

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	452000	1			T1	41		T2	75		T3	2
valid_sources[0x01]	471510	1			T1	76		T2	100		T3	1
valid_sources[0x02]	402092	1			T1	43		T2	92		T3	96
valid_sources[0x03]	402852	1			T1	46		T2	103		T4	11
valid_sources[0x04]	437104	1			T1	52		T2	101		T3	5183
valid_sources[0x05]	418664	1			T1	47		T2	81		T3	24
valid_sources[0x06]	427772	1			T1	27		T2	87		T3	45
valid_sources[0x07]	435405	1			T1	47		T2	90		T3	5
valid_sources[0x08]	448903	1			T1	41		T2	88		T4	8
valid_sources[0x09]	416030	1			T1	43		T2	93		T3	1
valid_sources[0x0a]	405859	1			T1	65		T2	93		T3	43
valid_sources[0x0b]	417733	1			T1	46		T2	93		T3	304
valid_sources[0x0c]	411594	1			T1	54		T2	83		T3	4
valid_sources[0x0d]	417879	1			T1	43		T2	90		T3	2
valid_sources[0x0e]	520176	1			T1	44		T2	89		T3	5
valid_sources[0x0f]	432858	1			T1	40		T2	89		T3	4479
valid_sources[0x10]	412428	1			T1	48		T2	97		T3	3294
valid_sources[0x11]	426579	1			T1	53		T2	90		T3	94
valid_sources[0x12]	422462	1			T1	34		T2	102		T3	23
valid_sources[0x13]	504722	1			T1	43		T2	94		T3	120
valid_sources[0x14]	397653	1			T1	60		T2	86		T3	4
valid_sources[0x15]	416087	1			T1	43		T2	94		T3	3373
valid_sources[0x16]	413481	1			T1	46		T2	71		T3	55
valid_sources[0x17]	613326	1			T1	36		T2	87		T3	127
valid_sources[0x18]	434581	1			T1	53		T2	93		T4	15
valid_sources[0x19]	404934	1			T1	50		T2	95		T3	229
valid_sources[0x1a]	414110	1			T1	45		T2	89		T3	1
valid_sources[0x1b]	440778	1			T1	48		T2	80		T3	120
valid_sources[0x1c]	414038	1			T1	35		T2	88		T3	10
valid_sources[0x1d]	405222	1			T1	54		T2	90		T3	30
valid_sources[0x1e]	415580	1			T1	50		T2	84		T3	6
valid_sources[0x1f]	424404	1			T1	39		T2	92		T3	1
valid_sources[0x20]	505412	1			T1	38		T2	83		T4	11
valid_sources[0x21]	422317	1			T1	67		T2	87		T3	1
valid_sources[0x22]	419001	1			T1	37		T2	64		T3	12
valid_sources[0x23]	390354	1			T1	37		T2	106		T3	5
valid_sources[0x24]	615893	1			T1	44		T2	89		T4	7
valid_sources[0x25]	419397	1			T1	43		T2	88		T3	5
valid_sources[0x26]	413890	1			T1	69		T2	92		T3	47
valid_sources[0x27]	426488	1			T1	31		T2	102		T3	89
valid_sources[0x28]	429868	1			T1	77		T2	75		T4	14
valid_sources[0x29]	479775	1			T1	53		T2	119		T3	35
valid_sources[0x2a]	590868	1			T1	50		T2	83		T3	784
valid_sources[0x2b]	417408	1			T1	45		T2	91		T3	3
valid_sources[0x2c]	424110	1			T1	50		T2	99		T3	45
valid_sources[0x2d]	402719	1			T1	46		T2	92		T3	36
valid_sources[0x2e]	464646	1			T1	51		T2	87		T3	85
valid_sources[0x2f]	487931	1			T1	40		T2	86		T4	1
valid_sources[0x30]	434864	1			T1	46		T2	87		T3	2
valid_sources[0x31]	497443	1			T1	50		T2	80		T3	6
valid_sources[0x32]	451015	1			T1	56		T2	77		T3	3250
valid_sources[0x33]	449519	1			T1	54		T2	82		T3	5
valid_sources[0x34]	429887	1			T1	37		T2	107		T3	4
valid_sources[0x35]	408308	1			T1	58		T2	103		T3	2
valid_sources[0x36]	415146	1			T1	55		T2	88		T3	3332
valid_sources[0x37]	412858	1			T1	46		T2	104		T3	37
valid_sources[0x38]	409292	1			T1	35		T2	73		T4	5
valid_sources[0x39]	416093	1			T1	27		T2	78		T3	103
valid_sources[0x3a]	398806	1			T1	30		T2	101		T3	49
valid_sources[0x3b]	432948	1			T1	38		T2	104		T3	3368
valid_sources[0x3c]	415143	1			T1	50		T2	76		T3	142
valid_sources[0x3d]	417156	1			T1	50		T2	86		T3	45
valid_sources[0x3e]	423195	1			T1	43		T2	82		T3	19
valid_sources[0x3f]	428309	1			T1	25		T2	90		T3	1825
valid_sources[0x40]	425541	1			T1	29		T2	87		T3	35
valid_sources[0x41]	422345	1			T1	34		T2	100		T4	15
valid_sources[0x42]	431694	1			T1	42		T2	91		T3	555
valid_sources[0x43]	414774	1			T1	54		T2	100		T3	8
valid_sources[0x44]	416246	1			T1	30		T2	80		T3	3067
valid_sources[0x45]	561419	1			T1	68		T2	95		T3	1
valid_sources[0x46]	455085	1			T1	33		T2	87		T3	1420
valid_sources[0x47]	512958	1			T1	49		T2	93		T4	7
valid_sources[0x48]	439784	1			T1	59		T2	87		T3	725
valid_sources[0x49]	400172	1			T1	40		T2	84		T3	4619
valid_sources[0x4a]	417258	1			T1	55		T2	83		T3	4538
valid_sources[0x4b]	444246	1			T1	52		T2	95		T3	48
valid_sources[0x4c]	460209	1			T1	56		T2	96		T3	89
valid_sources[0x4d]	399218	1			T1	54		T2	82		T4	13
valid_sources[0x4e]	491191	1			T1	48		T2	87		T4	15
valid_sources[0x4f]	466553	1			T1	33		T2	86		T3	2096
valid_sources[0x50]	405599	1			T1	53		T2	82		T3	4
valid_sources[0x51]	445992	1			T1	43		T2	83		T3	126
valid_sources[0x52]	447104	1			T1	43		T2	82		T3	1
valid_sources[0x53]	439663	1			T1	53		T2	92		T4	10
valid_sources[0x54]	422967	1			T1	49		T2	104		T3	1
valid_sources[0x55]	425416	1			T1	62		T2	78		T3	1
valid_sources[0x56]	427869	1			T1	58		T2	88		T3	1
valid_sources[0x57]	400833	1			T1	46		T2	92		T4	6
valid_sources[0x58]	408741	1			T1	38		T2	96		T3	16
valid_sources[0x59]	443848	1			T1	37		T2	94		T3	67
valid_sources[0x5a]	433879	1			T1	39		T2	100		T3	68
valid_sources[0x5b]	404489	1			T1	31		T2	87		T3	2
valid_sources[0x5c]	450517	1			T1	57		T2	76		T3	101
valid_sources[0x5d]	456147	1			T1	51		T2	87		T3	136
valid_sources[0x5e]	425740	1			T1	42		T2	70		T3	2984
valid_sources[0x5f]	710916	1			T1	48		T2	103		T3	1
valid_sources[0x60]	408650	1			T1	35		T2	108		T3	9
valid_sources[0x61]	433673	1			T1	35		T2	88		T3	2
valid_sources[0x62]	411474	1			T1	50		T2	94		T4	3
valid_sources[0x63]	427887	1			T1	40		T2	100		T3	110
valid_sources[0x64]	460736	1			T1	50		T2	104		T3	1251
valid_sources[0x65]	465730	1			T1	41		T2	107		T4	22
valid_sources[0x66]	419080	1			T1	42		T2	80		T3	1
valid_sources[0x67]	528076	1			T1	58		T2	69		T4	12
valid_sources[0x68]	424511	1			T1	34		T2	79		T3	1
valid_sources[0x69]	472519	1			T1	59		T2	88		T3	59
valid_sources[0x6a]	420140	1			T1	51		T2	102		T3	7
valid_sources[0x6b]	411730	1			T1	52		T2	102		T3	21
valid_sources[0x6c]	396133	1			T1	60		T2	71		T3	29
valid_sources[0x6d]	429653	1			T1	37		T2	87		T3	117
valid_sources[0x6e]	495049	1			T1	46		T2	78		T4	8
valid_sources[0x6f]	425873	1			T1	42		T2	90		T3	2290
valid_sources[0x70]	421324	1			T1	46		T2	68		T3	2
valid_sources[0x71]	452870	1			T1	62		T2	101		T4	12
valid_sources[0x72]	481105	1			T1	32		T2	81		T3	119
valid_sources[0x73]	498729	1			T1	35		T2	105		T3	43
valid_sources[0x74]	454726	1			T1	47		T2	89		T3	14
valid_sources[0x75]	504033	1			T1	33		T2	79		T3	49
valid_sources[0x76]	447969	1			T1	48		T2	81		T3	7
valid_sources[0x77]	434563	1			T1	40		T2	75		T3	1
valid_sources[0x78]	555213	1			T1	58		T2	79		T3	54
valid_sources[0x79]	430352	1			T1	36		T2	87		T3	27
valid_sources[0x7a]	443251	1			T1	47		T2	99		T3	67
valid_sources[0x7b]	409905	1			T1	55		T2	81		T3	1867
valid_sources[0x7c]	412554	1			T1	72		T2	77		T4	20
valid_sources[0x7d]	416998	1			T1	54		T2	87		T3	89
valid_sources[0x7e]	498660	1			T1	32		T2	89		T3	1
valid_sources[0x7f]	413684	1			T1	36		T2	99		T3	644
valid_sources[0x80]	401507	1			T1	47		T2	101		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22295575

1

T1

26

T2

41

T3

66755

values[0x0]

all_enables

biggest_size

4624536

1

T1

58

T2

100

T3

159

values[0x1]

all_enables

biggest_size

4562886

1

T1

36

T2

42

T3

75