Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15080210	0	0
ctrl_rd_A	2147483647	311428	0	0
intr_enable_rd_A	2147483647	276654	0	0
ovrd_rd_A	2147483647	308768	0	0
timeout_ctrl_rd_A	2147483647	309249	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15080210	0	0
T17	684966	282797	0	0
T20	132001	0	0	0
T22	601841	0	0	0
T23	0	76122	0	0
T24	121141	0	0	0
T25	804243	17796	0	0
T28	153299	0	0	0
T33	0	91160	0	0
T34	0	94131	0	0
T35	0	158816	0	0
T36	0	233153	0	0
T37	0	83643	0	0
T38	0	177281	0	0
T39	0	79624	0	0
T40	231219	0	0	0
T41	273183	0	0	0
T42	159625	0	0	0
T43	42724	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	311428	0	0
T23	0	8810	0	0
T25	804243	2082	0	0
T34	0	11127	0	0
T35	0	17581	0	0
T39	0	9024	0	0
T43	42724	0	0	0
T46	147880	0	0	0
T47	930127	0	0	0
T48	218896	0	0	0
T49	321390	0	0	0
T59	0	2807	0	0
T60	0	6044	0	0
T117	0	5642	0	0
T118	0	6797	0	0
T119	0	18930	0	0
T120	70636	0	0	0
T121	217767	0	0	0
T122	292708	0	0	0
T123	333735	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	276654	0	0
T23	0	8072	0	0
T25	804243	1814	0	0
T34	0	10121	0	0
T35	0	15843	0	0
T39	0	7898	0	0
T43	42724	0	0	0
T46	147880	0	0	0
T47	930127	0	0	0
T48	218896	0	0	0
T49	321390	0	0	0
T59	0	2568	0	0
T60	0	5294	0	0
T117	0	5096	0	0
T118	0	5585	0	0
T120	70636	0	0	0
T121	217767	0	0	0
T122	292708	0	0	0
T123	333735	0	0	0
T124	0	6	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	308768	0	0
T23	0	8529	0	0
T25	804243	1866	0	0
T34	0	10570	0	0
T35	0	17916	0	0
T39	0	8824	0	0
T43	42724	0	0	0
T46	147880	0	0	0
T47	930127	0	0	0
T48	218896	0	0	0
T49	321390	0	0	0
T59	0	3000	0	0
T60	0	6044	0	0
T117	0	5597	0	0
T118	0	6752	0	0
T119	0	18399	0	0
T120	70636	0	0	0
T121	217767	0	0	0
T122	292708	0	0	0
T123	333735	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	309249	0	0
T23	0	8573	0	0
T25	804243	1735	0	0
T34	0	10624	0	0
T35	0	18223	0	0
T39	0	9040	0	0
T43	42724	0	0	0
T46	147880	0	0	0
T47	930127	0	0	0
T48	218896	0	0	0
T49	321390	0	0	0
T59	0	3089	0	0
T60	0	6336	0	0
T117	0	5794	0	0
T118	0	6785	0	0
T119	0	19011	0	0
T120	70636	0	0	0
T121	217767	0	0	0
T122	292708	0	0	0
T123	333735	0	0	0