Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 64206683 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 21963795 1 T1 127 T2 267 T3 292



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 80791024 1 T1 844 T2 77662 T3 32076
values[0x0] 2551879 1 T1 159 T2 241 T3 265
values[0x1] 2827575 1 T1 157 T2 208 T3 286



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 44630414 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 41540064 1 T1 422 T2 26104 T3 11113



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 322086 1 T1 6 T2 350 T3 116
valid_sources[0x01] 386816 1 T2 495 T3 114 T6 57
valid_sources[0x02] 308189 1 T2 212 T3 132 T6 41
valid_sources[0x03] 367038 1 T2 334 T3 132 T6 40
valid_sources[0x04] 329436 1 T2 456 T3 139 T6 39
valid_sources[0x05] 318639 1 T2 361 T3 126 T6 67
valid_sources[0x06] 511601 1 T2 302 T3 130 T6 34
valid_sources[0x07] 339236 1 T1 44 T2 244 T3 128
valid_sources[0x08] 320779 1 T2 274 T3 129 T6 43
valid_sources[0x09] 398302 1 T2 246 T3 90 T6 52
valid_sources[0x0a] 330181 1 T2 443 T3 122 T6 55
valid_sources[0x0b] 332470 1 T1 17 T2 365 T3 117
valid_sources[0x0c] 358478 1 T2 352 T3 123 T6 64
valid_sources[0x0d] 339144 1 T1 28 T2 227 T3 112
valid_sources[0x0e] 313000 1 T2 230 T3 157 T6 77
valid_sources[0x0f] 330661 1 T2 241 T3 120 T6 37
valid_sources[0x10] 345267 1 T2 302 T3 128 T6 52
valid_sources[0x11] 350896 1 T1 1 T2 413 T3 136
valid_sources[0x12] 321971 1 T2 269 T3 133 T6 53
valid_sources[0x13] 347703 1 T2 321 T3 114 T6 39
valid_sources[0x14] 289588 1 T2 257 T3 155 T6 70
valid_sources[0x15] 298045 1 T2 309 T3 130 T6 58
valid_sources[0x16] 346996 1 T2 321 T3 115 T6 19
valid_sources[0x17] 362636 1 T2 355 T3 104 T6 52
valid_sources[0x18] 363115 1 T2 238 T3 125 T6 56
valid_sources[0x19] 319591 1 T2 230 T3 125 T6 38
valid_sources[0x1a] 305115 1 T2 258 T3 114 T6 51
valid_sources[0x1b] 346927 1 T2 145 T3 129 T4 10
valid_sources[0x1c] 360665 1 T2 265 T3 113 T6 26
valid_sources[0x1d] 411086 1 T2 216 T3 132 T6 106
valid_sources[0x1e] 319637 1 T2 313 T3 125 T6 54
valid_sources[0x1f] 317890 1 T2 279 T3 146 T6 44
valid_sources[0x20] 473346 1 T2 329 T3 122 T6 51
valid_sources[0x21] 314639 1 T1 17 T2 291 T3 116
valid_sources[0x22] 326453 1 T1 16 T2 274 T3 120
valid_sources[0x23] 316829 1 T2 240 T3 108 T6 62
valid_sources[0x24] 335241 1 T2 349 T3 133 T6 76
valid_sources[0x25] 369105 1 T2 193 T3 124 T6 29
valid_sources[0x26] 360574 1 T1 7 T2 214 T3 123
valid_sources[0x27] 315350 1 T2 267 T3 114 T6 87
valid_sources[0x28] 318819 1 T2 415 T3 128 T6 49
valid_sources[0x29] 375782 1 T1 14 T2 285 T3 109
valid_sources[0x2a] 325360 1 T2 222 T3 120 T6 19
valid_sources[0x2b] 398114 1 T2 381 T3 148 T6 46
valid_sources[0x2c] 325008 1 T1 13 T2 228 T3 138
valid_sources[0x2d] 311260 1 T2 374 T3 138 T6 74
valid_sources[0x2e] 375488 1 T1 11 T2 375 T3 119
valid_sources[0x2f] 303175 1 T2 182 T3 118 T6 49
valid_sources[0x30] 322347 1 T1 32 T2 221 T3 136
valid_sources[0x31] 381545 1 T1 42 T2 350 T3 120
valid_sources[0x32] 417691 1 T2 254 T3 116 T6 45
valid_sources[0x33] 308385 1 T2 284 T3 118 T6 88
valid_sources[0x34] 335430 1 T2 354 T3 126 T6 67
valid_sources[0x35] 336337 1 T1 11 T2 242 T3 112
valid_sources[0x36] 313107 1 T2 331 T3 129 T6 38
valid_sources[0x37] 333829 1 T2 248 T3 127 T6 59
valid_sources[0x38] 300305 1 T2 216 T3 142 T6 42
valid_sources[0x39] 303338 1 T1 9 T2 291 T3 100
valid_sources[0x3a] 304379 1 T2 274 T3 140 T6 45
valid_sources[0x3b] 308964 1 T2 360 T3 133 T6 27
valid_sources[0x3c] 311564 1 T2 339 T3 135 T6 40
valid_sources[0x3d] 329304 1 T2 320 T3 132 T6 34
valid_sources[0x3e] 335461 1 T1 13 T2 320 T3 122
valid_sources[0x3f] 301140 1 T2 359 T3 145 T6 64
valid_sources[0x40] 314107 1 T2 575 T3 131 T6 38
valid_sources[0x41] 324553 1 T2 221 T3 121 T6 20
valid_sources[0x42] 363363 1 T2 296 T3 109 T4 10
valid_sources[0x43] 343034 1 T2 262 T3 100 T6 53
valid_sources[0x44] 323064 1 T2 156 T3 120 T6 55
valid_sources[0x45] 332716 1 T2 259 T3 113 T6 57
valid_sources[0x46] 315520 1 T2 297 T3 118 T6 43
valid_sources[0x47] 311785 1 T2 202 T3 134 T6 43
valid_sources[0x48] 332201 1 T2 445 T3 138 T6 95
valid_sources[0x49] 303506 1 T2 221 T3 138 T6 84
valid_sources[0x4a] 309518 1 T2 382 T3 132 T6 35
valid_sources[0x4b] 311421 1 T2 259 T3 119 T6 79
valid_sources[0x4c] 318680 1 T2 268 T3 134 T6 76
valid_sources[0x4d] 299359 1 T2 378 T3 136 T6 48
valid_sources[0x4e] 380895 1 T1 13 T2 276 T3 145
valid_sources[0x4f] 323094 1 T2 183 T3 144 T6 54
valid_sources[0x50] 303615 1 T2 232 T3 141 T6 66
valid_sources[0x51] 313958 1 T2 404 T3 134 T6 101
valid_sources[0x52] 303090 1 T2 349 T3 135 T6 96
valid_sources[0x53] 308699 1 T2 379 T3 121 T6 40
valid_sources[0x54] 318914 1 T1 17 T2 275 T3 108
valid_sources[0x55] 372515 1 T2 298 T3 107 T6 49
valid_sources[0x56] 347135 1 T2 319 T3 145 T6 42
valid_sources[0x57] 318072 1 T2 329 T3 125 T6 29
valid_sources[0x58] 327281 1 T2 356 T3 148 T6 89
valid_sources[0x59] 325624 1 T2 332 T3 140 T6 42
valid_sources[0x5a] 297241 1 T2 337 T3 115 T6 37
valid_sources[0x5b] 319624 1 T2 331 T3 131 T6 38
valid_sources[0x5c] 341811 1 T2 207 T3 141 T6 48
valid_sources[0x5d] 297280 1 T2 280 T3 138 T6 57
valid_sources[0x5e] 425047 1 T1 27 T2 336 T3 135
valid_sources[0x5f] 297409 1 T2 349 T3 101 T6 43
valid_sources[0x60] 428185 1 T2 298 T3 157 T6 24
valid_sources[0x61] 321670 1 T1 3 T2 253 T3 120
valid_sources[0x62] 324949 1 T2 314 T3 130 T6 88
valid_sources[0x63] 304243 1 T2 332 T3 122 T6 63
valid_sources[0x64] 295970 1 T1 2 T2 309 T3 127
valid_sources[0x65] 301612 1 T2 257 T3 139 T6 35
valid_sources[0x66] 310749 1 T2 362 T3 130 T6 64
valid_sources[0x67] 348788 1 T1 15 T2 254 T3 121
valid_sources[0x68] 456483 1 T2 214 T3 103 T6 51
valid_sources[0x69] 319342 1 T1 4 T2 424 T3 131
valid_sources[0x6a] 296661 1 T1 33 T2 356 T3 112
valid_sources[0x6b] 489732 1 T1 38 T2 324 T3 141
valid_sources[0x6c] 309872 1 T2 349 T3 145 T6 47
valid_sources[0x6d] 448021 1 T2 442 T3 124 T6 52
valid_sources[0x6e] 368836 1 T1 6 T2 332 T3 133
valid_sources[0x6f] 400584 1 T2 370 T3 138 T6 70
valid_sources[0x70] 311670 1 T2 229 T3 107 T6 33
valid_sources[0x71] 308120 1 T2 281 T3 153 T6 60
valid_sources[0x72] 312859 1 T2 252 T3 123 T6 17
valid_sources[0x73] 299778 1 T2 318 T3 169 T6 51
valid_sources[0x74] 383952 1 T2 349 T3 132 T6 46
valid_sources[0x75] 407834 1 T2 289 T3 139 T6 71
valid_sources[0x76] 308449 1 T1 3 T2 285 T3 136
valid_sources[0x77] 330078 1 T2 221 T3 139 T4 5
valid_sources[0x78] 303447 1 T2 322 T3 123 T6 40
valid_sources[0x79] 519307 1 T2 301 T3 124 T6 60
valid_sources[0x7a] 304584 1 T2 290 T3 143 T6 74
valid_sources[0x7b] 400879 1 T2 228 T3 127 T6 24
valid_sources[0x7c] 309166 1 T2 160 T3 135 T6 37
valid_sources[0x7d] 307902 1 T2 354 T3 116 T6 83
valid_sources[0x7e] 338922 1 T2 481 T3 112 T6 31
valid_sources[0x7f] 327401 1 T2 252 T3 137 T6 43
valid_sources[0x80] 306071 1 T1 9 T2 243 T3 133



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 17331509 1 T1 42 T2 137 T3 122
values[0x0] all_enables biggest_size 2342611 1 T1 52 T2 91 T3 94
values[0x1] all_enables biggest_size 2289675 1 T1 33 T2 39 T3 76

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%