Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	7411898	0	0
ctrl_rd_A	2147483647	204741	0	0
intr_enable_rd_A	2147483647	182223	0	0
ovrd_rd_A	2147483647	203441	0	0
timeout_ctrl_rd_A	2147483647	204972	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7411898	0	0
T27	120687	302905	0	0
T28	0	170686	0	0
T29	0	53539	0	0
T30	5932	0	0	0
T36	0	87698	0	0
T37	0	41253	0	0
T38	0	199774	0	0
T39	0	182679	0	0
T40	0	179758	0	0
T41	0	177535	0	0
T42	0	156264	0	0
T43	230796	0	0	0
T44	117400	0	0	0
T45	521586	0	0	0
T46	121476	0	0	0
T47	354677	0	0	0
T48	920061	0	0	0
T49	41548	0	0	0
T50	540311	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	204741	0	0
T27	120687	16705	0	0
T30	5932	0	0	0
T41	0	7840	0	0
T42	0	12614	0	0
T43	230796	0	0	0
T44	117400	0	0	0
T45	521586	0	0	0
T46	121476	0	0	0
T47	354677	0	0	0
T48	920061	0	0	0
T49	41548	0	0	0
T50	540311	0	0	0
T102	0	3952	0	0
T103	0	18768	0	0
T104	0	4943	0	0
T105	0	7686	0	0
T106	0	3627	0	0
T107	0	15062	0	0
T108	0	7916	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	182223	0	0
T19	590741	7	0	0
T27	120687	13736	0	0
T41	0	6932	0	0
T42	0	11154	0	0
T43	230796	0	0	0
T44	117400	0	0	0
T45	521586	0	0	0
T84	222333	0	0	0
T102	0	3406	0	0
T103	0	17302	0	0
T104	0	4862	0	0
T105	0	6694	0	0
T109	0	22	0	0
T110	0	11	0	0
T111	179576	0	0	0
T112	164206	0	0	0
T113	547453	0	0	0
T114	158160	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	203441	0	0
T27	120687	15554	0	0
T30	5932	0	0	0
T41	0	8222	0	0
T42	0	12632	0	0
T43	230796	0	0	0
T44	117400	0	0	0
T45	521586	0	0	0
T46	121476	0	0	0
T47	354677	0	0	0
T48	920061	0	0	0
T49	41548	0	0	0
T50	540311	0	0	0
T102	0	3992	0	0
T103	0	18770	0	0
T104	0	5398	0	0
T105	0	7782	0	0
T106	0	3553	0	0
T107	0	15409	0	0
T108	0	8157	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	204972	0	0
T27	120687	15818	0	0
T30	5932	0	0	0
T41	0	7954	0	0
T42	0	12893	0	0
T43	230796	0	0	0
T44	117400	0	0	0
T45	521586	0	0	0
T46	121476	0	0	0
T47	354677	0	0	0
T48	920061	0	0	0
T49	41548	0	0	0
T50	540311	0	0	0
T102	0	3778	0	0
T103	0	19265	0	0
T104	0	4937	0	0
T105	0	7898	0	0
T106	0	3459	0	0
T107	0	15004	0	0
T108	0	8231	0	0