Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62191580	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

18662309

1

T1

141

T2

30

T3

77

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	74932844	1			T1	30398		T2	16881		T3	6424
values[0x0]	2801467	1			T1	90		T2	33		T3	35
values[0x1]	3119578	1			T1	76		T2	25		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42775079	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38078810

1

T1

10205

T2

5689

T3

2233

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	285507	1			T1	115		T2	43		T3	30
valid_sources[0x01]	276802	1			T1	128		T2	52		T3	15
valid_sources[0x02]	340972	1			T1	108		T2	55		T3	27
valid_sources[0x03]	291968	1			T1	98		T2	37		T3	23
valid_sources[0x04]	324722	1			T1	114		T2	40		T3	22
valid_sources[0x05]	272847	1			T1	155		T2	67		T3	20
valid_sources[0x06]	286465	1			T1	125		T2	53		T3	21
valid_sources[0x07]	284381	1			T1	116		T2	50		T3	31
valid_sources[0x08]	416686	1			T1	128		T2	51		T3	31
valid_sources[0x09]	282614	1			T1	109		T2	64		T3	19
valid_sources[0x0a]	376088	1			T1	111		T2	51		T3	38
valid_sources[0x0b]	277045	1			T1	120		T2	98		T3	39
valid_sources[0x0c]	324121	1			T1	95		T2	64		T3	24
valid_sources[0x0d]	294649	1			T1	88		T2	55		T3	31
valid_sources[0x0e]	305064	1			T1	126		T2	92		T3	29
valid_sources[0x0f]	302144	1			T1	122		T2	105		T3	12
valid_sources[0x10]	288732	1			T1	131		T2	26		T3	24
valid_sources[0x11]	341587	1			T1	146		T2	93		T3	9
valid_sources[0x12]	271182	1			T1	119		T2	36		T3	31
valid_sources[0x13]	303756	1			T1	91		T2	100		T3	22
valid_sources[0x14]	306389	1			T1	151		T2	77		T3	24
valid_sources[0x15]	316645	1			T1	120		T2	85		T3	33
valid_sources[0x16]	296644	1			T1	137		T2	26		T3	23
valid_sources[0x17]	322924	1			T1	127		T2	84		T3	30
valid_sources[0x18]	297529	1			T1	104		T2	39		T3	34
valid_sources[0x19]	341329	1			T1	111		T2	80		T3	25
valid_sources[0x1a]	387398	1			T1	111		T2	51		T3	10
valid_sources[0x1b]	311936	1			T1	126		T2	53		T3	23
valid_sources[0x1c]	274785	1			T1	107		T2	45		T3	29
valid_sources[0x1d]	368552	1			T1	95		T2	82		T3	19
valid_sources[0x1e]	312841	1			T1	123		T2	90		T3	33
valid_sources[0x1f]	289356	1			T1	94		T2	60		T3	16
valid_sources[0x20]	291089	1			T1	129		T2	49		T3	32
valid_sources[0x21]	317290	1			T1	97		T2	57		T3	21
valid_sources[0x22]	560880	1			T1	109		T2	76		T3	29
valid_sources[0x23]	275072	1			T1	132		T2	79		T3	32
valid_sources[0x24]	399008	1			T1	93		T2	76		T3	37
valid_sources[0x25]	304305	1			T1	166		T2	72		T3	15
valid_sources[0x26]	293069	1			T1	90		T2	45		T3	31
valid_sources[0x27]	276297	1			T1	93		T2	75		T3	20
valid_sources[0x28]	318377	1			T1	109		T2	161		T3	37
valid_sources[0x29]	310217	1			T1	124		T2	81		T3	15
valid_sources[0x2a]	306023	1			T1	148		T2	93		T3	19
valid_sources[0x2b]	290280	1			T1	138		T2	115		T3	41
valid_sources[0x2c]	305814	1			T1	122		T2	59		T3	23
valid_sources[0x2d]	286515	1			T1	119		T2	40		T3	15
valid_sources[0x2e]	280899	1			T1	144		T2	60		T3	19
valid_sources[0x2f]	385986	1			T1	135		T2	89		T3	22
valid_sources[0x30]	305074	1			T1	130		T2	52		T3	32
valid_sources[0x31]	336844	1			T1	117		T2	22		T3	29
valid_sources[0x32]	291001	1			T1	127		T2	60		T3	29
valid_sources[0x33]	287671	1			T1	128		T2	71		T3	28
valid_sources[0x34]	330371	1			T1	109		T2	75		T3	24
valid_sources[0x35]	409393	1			T1	96		T2	40		T3	36
valid_sources[0x36]	298806	1			T1	130		T2	77		T3	26
valid_sources[0x37]	325655	1			T1	111		T2	92		T3	23
valid_sources[0x38]	326396	1			T1	129		T2	56		T3	26
valid_sources[0x39]	309872	1			T1	116		T2	130		T3	31
valid_sources[0x3a]	515619	1			T1	101		T2	81		T3	33
valid_sources[0x3b]	303402	1			T1	108		T2	59		T3	14
valid_sources[0x3c]	285323	1			T1	130		T2	27		T3	13
valid_sources[0x3d]	299921	1			T1	117		T2	72		T3	21
valid_sources[0x3e]	329631	1			T1	121		T2	40		T3	28
valid_sources[0x3f]	310581	1			T1	113		T2	43		T3	22
valid_sources[0x40]	285383	1			T1	122		T2	57		T3	39
valid_sources[0x41]	320284	1			T1	125		T2	84		T3	33
valid_sources[0x42]	313176	1			T1	103		T2	95		T3	23
valid_sources[0x43]	302629	1			T1	138		T2	99		T3	13
valid_sources[0x44]	349375	1			T1	136		T2	88		T3	18
valid_sources[0x45]	299896	1			T1	162		T2	35		T3	19
valid_sources[0x46]	301309	1			T1	144		T2	99		T3	34
valid_sources[0x47]	309297	1			T1	114		T2	86		T3	10
valid_sources[0x48]	293587	1			T1	136		T2	72		T3	33
valid_sources[0x49]	293248	1			T1	139		T2	40		T3	28
valid_sources[0x4a]	287090	1			T1	121		T2	87		T3	21
valid_sources[0x4b]	313396	1			T1	133		T2	45		T3	31
valid_sources[0x4c]	328405	1			T1	134		T2	51		T3	21
valid_sources[0x4d]	310979	1			T1	131		T2	10		T3	20
valid_sources[0x4e]	340304	1			T1	115		T2	20		T3	27
valid_sources[0x4f]	298438	1			T1	126		T2	45		T3	28
valid_sources[0x50]	289148	1			T1	131		T2	30		T3	24
valid_sources[0x51]	299948	1			T1	88		T2	89		T3	20
valid_sources[0x52]	381242	1			T1	106		T2	73		T3	23
valid_sources[0x53]	306153	1			T1	106		T2	67		T3	29
valid_sources[0x54]	309885	1			T1	124		T2	54		T3	31
valid_sources[0x55]	293058	1			T1	106		T2	57		T3	22
valid_sources[0x56]	293514	1			T1	84		T2	47		T3	18
valid_sources[0x57]	330534	1			T1	105		T2	96		T3	21
valid_sources[0x58]	327786	1			T1	150		T2	46		T3	31
valid_sources[0x59]	318818	1			T1	139		T2	61		T3	22
valid_sources[0x5a]	281693	1			T1	110		T2	17		T3	33
valid_sources[0x5b]	284864	1			T1	122		T2	49		T3	29
valid_sources[0x5c]	312468	1			T1	115		T2	64		T3	23
valid_sources[0x5d]	285875	1			T1	114		T2	82		T3	28
valid_sources[0x5e]	357700	1			T1	123		T2	54		T3	24
valid_sources[0x5f]	301897	1			T1	143		T2	80		T3	32
valid_sources[0x60]	612613	1			T1	123		T2	76		T3	54
valid_sources[0x61]	297804	1			T1	112		T2	66		T3	27
valid_sources[0x62]	271309	1			T1	125		T2	64		T3	20
valid_sources[0x63]	301278	1			T1	110		T2	64		T3	33
valid_sources[0x64]	306746	1			T1	130		T2	79		T3	27
valid_sources[0x65]	319863	1			T1	130		T2	87		T3	24
valid_sources[0x66]	304876	1			T1	128		T2	106		T3	13
valid_sources[0x67]	285161	1			T1	117		T2	58		T3	27
valid_sources[0x68]	280821	1			T1	88		T2	55		T3	29
valid_sources[0x69]	464653	1			T1	116		T2	132		T3	33
valid_sources[0x6a]	316861	1			T1	153		T2	38		T3	34
valid_sources[0x6b]	291923	1			T1	94		T2	102		T3	34
valid_sources[0x6c]	355473	1			T1	112		T2	94		T3	4
valid_sources[0x6d]	296246	1			T1	121		T2	61		T3	17
valid_sources[0x6e]	297821	1			T1	109		T2	46		T3	21
valid_sources[0x6f]	279761	1			T1	130		T2	44		T3	18
valid_sources[0x70]	379706	1			T1	102		T2	41		T3	19
valid_sources[0x71]	295916	1			T1	98		T2	46		T3	18
valid_sources[0x72]	321844	1			T1	78		T2	134		T3	14
valid_sources[0x73]	270394	1			T1	106		T2	34		T3	29
valid_sources[0x74]	304084	1			T1	138		T2	38		T3	7
valid_sources[0x75]	283654	1			T1	93		T2	64		T3	9
valid_sources[0x76]	299219	1			T1	134		T2	86		T3	23
valid_sources[0x77]	341799	1			T1	94		T2	74		T3	29
valid_sources[0x78]	288009	1			T1	139		T2	77		T3	49
valid_sources[0x79]	328702	1			T1	118		T2	32		T3	22
valid_sources[0x7a]	293087	1			T1	96		T2	84		T3	26
valid_sources[0x7b]	312031	1			T1	134		T2	68		T3	21
valid_sources[0x7c]	289420	1			T1	94		T2	49		T3	33
valid_sources[0x7d]	301773	1			T1	135		T2	77		T3	33
valid_sources[0x7e]	318452	1			T1	115		T2	49		T3	41
valid_sources[0x7f]	308737	1			T1	103		T2	53		T3	19
valid_sources[0x80]	289014	1			T1	95		T2	79		T3	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13509239

1

T1

84

T2

6

T3

47

values[0x0]

all_enables

biggest_size

2598994

1

T1

39

T2

12

T3

19

values[0x1]

all_enables

biggest_size

2554076

1

T1

18

T2

12

T3

11