Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	8447089	0	0
ctrl_rd_A	2147483647	133328	0	0
intr_enable_rd_A	2147483647	117246	0	0
ovrd_rd_A	2147483647	132500	0	0
timeout_ctrl_rd_A	2147483647	132521	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8447089	0	0
T8	290638	119262	0	0
T9	625111	0	0	0
T10	26652	0	0	0
T11	209049	0	0	0
T12	871490	0	0	0
T13	0	48836	0	0
T14	28579	0	0	0
T16	0	240002	0	0
T18	640413	0	0	0
T30	0	44412	0	0
T31	0	23200	0	0
T32	0	125443	0	0
T33	0	43276	0	0
T34	0	143089	0	0
T35	0	43399	0	0
T36	0	67347	0	0
T37	349679	0	0	0
T38	187811	0	0	0
T39	131853	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	133328	0	0
T25	1574	0	0	0
T26	1063	0	0	0
T31	902982	2581	0	0
T32	304541	0	0	0
T35	0	4933	0	0
T46	0	5291	0	0
T57	0	9249	0	0
T68	0	7838	0	0
T100	0	15713	0	0
T101	0	3082	0	0
T102	0	8449	0	0
T103	0	4025	0	0
T104	0	12204	0	0
T105	177035	0	0	0
T106	156465	0	0	0
T107	209939	0	0	0
T108	241322	0	0	0
T109	892922	0	0	0
T110	103391	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117246	0	0
T25	1574	0	0	0
T26	1063	0	0	0
T31	902982	2143	0	0
T32	304541	0	0	0
T35	0	4317	0	0
T46	0	4574	0	0
T100	0	13744	0	0
T101	0	2470	0	0
T102	0	7441	0	0
T103	0	3549	0	0
T104	0	10452	0	0
T105	177035	0	0	0
T106	156465	0	0	0
T107	209939	0	0	0
T108	241322	0	0	0
T109	892922	0	0	0
T110	103391	0	0	0
T111	0	6	0	0
T112	0	4	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	132500	0	0
T25	1574	0	0	0
T26	1063	0	0	0
T31	902982	2254	0	0
T32	304541	0	0	0
T35	0	4908	0	0
T46	0	5092	0	0
T57	0	9237	0	0
T68	0	7860	0	0
T100	0	16057	0	0
T101	0	2634	0	0
T102	0	8098	0	0
T103	0	4007	0	0
T104	0	12386	0	0
T105	177035	0	0	0
T106	156465	0	0	0
T107	209939	0	0	0
T108	241322	0	0	0
T109	892922	0	0	0
T110	103391	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	132521	0	0
T25	1574	0	0	0
T26	1063	0	0	0
T31	902982	2368	0	0
T32	304541	0	0	0
T35	0	5210	0	0
T46	0	5216	0	0
T57	0	9128	0	0
T68	0	8043	0	0
T100	0	15578	0	0
T101	0	2831	0	0
T102	0	8249	0	0
T103	0	3762	0	0
T104	0	12037	0	0
T105	177035	0	0	0
T106	156465	0	0	0
T107	209939	0	0	0
T108	241322	0	0	0
T109	892922	0	0	0
T110	103391	0	0	0