Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9144544	0	0
ctrl_rd_A	2147483647	236931	0	0
intr_enable_rd_A	2147483647	214144	0	0
ovrd_rd_A	2147483647	237344	0	0
timeout_ctrl_rd_A	2147483647	239275	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9144544	0	0
T13	795950	302150	0	0
T19	0	35032	0	0
T22	0	197305	0	0
T29	0	93396	0	0
T30	0	53781	0	0
T31	0	105127	0	0
T32	0	92833	0	0
T33	0	66469	0	0
T34	0	150102	0	0
T35	0	214901	0	0
T36	258327	0	0	0
T37	118733	0	0	0
T38	575698	0	0	0
T39	177654	0	0	0
T40	241553	0	0	0
T41	692662	0	0	0
T42	331744	0	0	0
T43	319258	0	0	0
T44	993729	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	236931	0	0
T30	166323	2313	0	0
T31	0	4372	0	0
T33	0	7199	0	0
T106	0	3350	0	0
T113	0	4337	0	0
T114	0	5922	0	0
T115	0	4561	0	0
T116	0	15075	0	0
T117	0	1691	0	0
T118	0	7352	0	0
T119	984697	0	0	0
T120	986897	0	0	0
T121	632329	0	0	0
T122	106060	0	0	0
T123	83118	0	0	0
T124	277385	0	0	0
T125	409897	0	0	0
T126	138106	0	0	0
T127	598827	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	214144	0	0
T30	166323	2099	0	0
T31	0	3933	0	0
T33	0	6447	0	0
T106	0	2970	0	0
T113	0	3767	0	0
T114	0	5128	0	0
T115	0	4034	0	0
T116	0	13986	0	0
T117	0	1759	0	0
T118	0	6424	0	0
T119	984697	0	0	0
T120	986897	0	0	0
T121	632329	0	0	0
T122	106060	0	0	0
T123	83118	0	0	0
T124	277385	0	0	0
T125	409897	0	0	0
T126	138106	0	0	0
T127	598827	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	237344	0	0
T30	166323	2558	0	0
T31	0	4455	0	0
T33	0	7318	0	0
T106	0	3335	0	0
T113	0	4223	0	0
T114	0	5682	0	0
T115	0	4531	0	0
T116	0	15798	0	0
T117	0	1863	0	0
T118	0	7192	0	0
T119	984697	0	0	0
T120	986897	0	0	0
T121	632329	0	0	0
T122	106060	0	0	0
T123	83118	0	0	0
T124	277385	0	0	0
T125	409897	0	0	0
T126	138106	0	0	0
T127	598827	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	239275	0	0
T30	166323	2539	0	0
T31	0	4736	0	0
T33	0	6992	0	0
T106	0	3519	0	0
T113	0	4144	0	0
T114	0	6142	0	0
T115	0	4697	0	0
T116	0	15461	0	0
T117	0	1854	0	0
T118	0	7373	0	0
T119	984697	0	0	0
T120	986897	0	0	0
T121	632329	0	0	0
T122	106060	0	0	0
T123	83118	0	0	0
T124	277385	0	0	0
T125	409897	0	0	0
T126	138106	0	0	0
T127	598827	0	0	0