Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1492422 |
577162 |
0 |
0 |
T2 |
241390 |
203302 |
0 |
0 |
T3 |
1299034 |
636027 |
0 |
0 |
T4 |
198358 |
32 |
0 |
0 |
T5 |
1294970 |
24108 |
0 |
0 |
T6 |
2806 |
0 |
0 |
0 |
T7 |
2214 |
0 |
0 |
0 |
T8 |
1010320 |
939079 |
0 |
0 |
T9 |
767740 |
575849 |
0 |
0 |
T10 |
331620 |
7186 |
0 |
0 |
T11 |
0 |
340572 |
0 |
0 |
T12 |
0 |
46 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1492422 |
1492366 |
0 |
0 |
T2 |
241390 |
241374 |
0 |
0 |
T3 |
1299034 |
1299002 |
0 |
0 |
T4 |
198358 |
198254 |
0 |
0 |
T5 |
1294970 |
1294776 |
0 |
0 |
T6 |
2806 |
2638 |
0 |
0 |
T7 |
2214 |
2098 |
0 |
0 |
T8 |
1010320 |
1010308 |
0 |
0 |
T9 |
767740 |
767714 |
0 |
0 |
T10 |
331620 |
331486 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1492422 |
1492366 |
0 |
0 |
T2 |
241390 |
241374 |
0 |
0 |
T3 |
1299034 |
1299002 |
0 |
0 |
T4 |
198358 |
198254 |
0 |
0 |
T5 |
1294970 |
1294776 |
0 |
0 |
T6 |
2806 |
2638 |
0 |
0 |
T7 |
2214 |
2098 |
0 |
0 |
T8 |
1010320 |
1010308 |
0 |
0 |
T9 |
767740 |
767714 |
0 |
0 |
T10 |
331620 |
331486 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1492422 |
1492366 |
0 |
0 |
T2 |
241390 |
241374 |
0 |
0 |
T3 |
1299034 |
1299002 |
0 |
0 |
T4 |
198358 |
198254 |
0 |
0 |
T5 |
1294970 |
1294776 |
0 |
0 |
T6 |
2806 |
2638 |
0 |
0 |
T7 |
2214 |
2098 |
0 |
0 |
T8 |
1010320 |
1010308 |
0 |
0 |
T9 |
767740 |
767714 |
0 |
0 |
T10 |
331620 |
331486 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1492422 |
577162 |
0 |
0 |
T2 |
241390 |
203302 |
0 |
0 |
T3 |
1299034 |
636027 |
0 |
0 |
T4 |
198358 |
32 |
0 |
0 |
T5 |
1294970 |
24108 |
0 |
0 |
T6 |
2806 |
0 |
0 |
0 |
T7 |
2214 |
0 |
0 |
0 |
T8 |
1010320 |
939079 |
0 |
0 |
T9 |
767740 |
575849 |
0 |
0 |
T10 |
331620 |
7186 |
0 |
0 |
T11 |
0 |
340572 |
0 |
0 |
T12 |
0 |
46 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T9 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1748980346 |
0 |
0 |
T1 |
746211 |
392694 |
0 |
0 |
T2 |
120695 |
138270 |
0 |
0 |
T3 |
649517 |
347833 |
0 |
0 |
T4 |
99179 |
2 |
0 |
0 |
T5 |
647485 |
10 |
0 |
0 |
T6 |
1403 |
0 |
0 |
0 |
T7 |
1107 |
0 |
0 |
0 |
T8 |
505160 |
97993 |
0 |
0 |
T9 |
383870 |
197057 |
0 |
0 |
T10 |
165810 |
10 |
0 |
0 |
T11 |
0 |
254387 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
746211 |
746183 |
0 |
0 |
T2 |
120695 |
120687 |
0 |
0 |
T3 |
649517 |
649501 |
0 |
0 |
T4 |
99179 |
99127 |
0 |
0 |
T5 |
647485 |
647388 |
0 |
0 |
T6 |
1403 |
1319 |
0 |
0 |
T7 |
1107 |
1049 |
0 |
0 |
T8 |
505160 |
505154 |
0 |
0 |
T9 |
383870 |
383857 |
0 |
0 |
T10 |
165810 |
165743 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
746211 |
746183 |
0 |
0 |
T2 |
120695 |
120687 |
0 |
0 |
T3 |
649517 |
649501 |
0 |
0 |
T4 |
99179 |
99127 |
0 |
0 |
T5 |
647485 |
647388 |
0 |
0 |
T6 |
1403 |
1319 |
0 |
0 |
T7 |
1107 |
1049 |
0 |
0 |
T8 |
505160 |
505154 |
0 |
0 |
T9 |
383870 |
383857 |
0 |
0 |
T10 |
165810 |
165743 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
746211 |
746183 |
0 |
0 |
T2 |
120695 |
120687 |
0 |
0 |
T3 |
649517 |
649501 |
0 |
0 |
T4 |
99179 |
99127 |
0 |
0 |
T5 |
647485 |
647388 |
0 |
0 |
T6 |
1403 |
1319 |
0 |
0 |
T7 |
1107 |
1049 |
0 |
0 |
T8 |
505160 |
505154 |
0 |
0 |
T9 |
383870 |
383857 |
0 |
0 |
T10 |
165810 |
165743 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1748980346 |
0 |
0 |
T1 |
746211 |
392694 |
0 |
0 |
T2 |
120695 |
138270 |
0 |
0 |
T3 |
649517 |
347833 |
0 |
0 |
T4 |
99179 |
2 |
0 |
0 |
T5 |
647485 |
10 |
0 |
0 |
T6 |
1403 |
0 |
0 |
0 |
T7 |
1107 |
0 |
0 |
0 |
T8 |
505160 |
97993 |
0 |
0 |
T9 |
383870 |
197057 |
0 |
0 |
T10 |
165810 |
10 |
0 |
0 |
T11 |
0 |
254387 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T13,T14 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T8,T13,T14 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
649812119 |
0 |
0 |
T1 |
746211 |
184468 |
0 |
0 |
T2 |
120695 |
65032 |
0 |
0 |
T3 |
649517 |
288194 |
0 |
0 |
T4 |
99179 |
30 |
0 |
0 |
T5 |
647485 |
24098 |
0 |
0 |
T6 |
1403 |
0 |
0 |
0 |
T7 |
1107 |
0 |
0 |
0 |
T8 |
505160 |
841086 |
0 |
0 |
T9 |
383870 |
378792 |
0 |
0 |
T10 |
165810 |
7176 |
0 |
0 |
T11 |
0 |
86185 |
0 |
0 |
T12 |
0 |
43 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
746211 |
746183 |
0 |
0 |
T2 |
120695 |
120687 |
0 |
0 |
T3 |
649517 |
649501 |
0 |
0 |
T4 |
99179 |
99127 |
0 |
0 |
T5 |
647485 |
647388 |
0 |
0 |
T6 |
1403 |
1319 |
0 |
0 |
T7 |
1107 |
1049 |
0 |
0 |
T8 |
505160 |
505154 |
0 |
0 |
T9 |
383870 |
383857 |
0 |
0 |
T10 |
165810 |
165743 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
746211 |
746183 |
0 |
0 |
T2 |
120695 |
120687 |
0 |
0 |
T3 |
649517 |
649501 |
0 |
0 |
T4 |
99179 |
99127 |
0 |
0 |
T5 |
647485 |
647388 |
0 |
0 |
T6 |
1403 |
1319 |
0 |
0 |
T7 |
1107 |
1049 |
0 |
0 |
T8 |
505160 |
505154 |
0 |
0 |
T9 |
383870 |
383857 |
0 |
0 |
T10 |
165810 |
165743 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
746211 |
746183 |
0 |
0 |
T2 |
120695 |
120687 |
0 |
0 |
T3 |
649517 |
649501 |
0 |
0 |
T4 |
99179 |
99127 |
0 |
0 |
T5 |
647485 |
647388 |
0 |
0 |
T6 |
1403 |
1319 |
0 |
0 |
T7 |
1107 |
1049 |
0 |
0 |
T8 |
505160 |
505154 |
0 |
0 |
T9 |
383870 |
383857 |
0 |
0 |
T10 |
165810 |
165743 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
649812119 |
0 |
0 |
T1 |
746211 |
184468 |
0 |
0 |
T2 |
120695 |
65032 |
0 |
0 |
T3 |
649517 |
288194 |
0 |
0 |
T4 |
99179 |
30 |
0 |
0 |
T5 |
647485 |
24098 |
0 |
0 |
T6 |
1403 |
0 |
0 |
0 |
T7 |
1107 |
0 |
0 |
0 |
T8 |
505160 |
841086 |
0 |
0 |
T9 |
383870 |
378792 |
0 |
0 |
T10 |
165810 |
7176 |
0 |
0 |
T11 |
0 |
86185 |
0 |
0 |
T12 |
0 |
43 |
0 |
0 |