Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9734974	0	0
ctrl_rd_A	2147483647	151242	0	0
intr_enable_rd_A	2147483647	133872	0	0
ovrd_rd_A	2147483647	149189	0	0
timeout_ctrl_rd_A	2147483647	149505	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9734974	0	0
T3	649517	251723	0	0
T4	99179	0	0	0
T5	647485	0	0	0
T6	1403	0	0	0
T7	1107	0	0	0
T8	505160	0	0	0
T9	383870	146269	0	0
T10	165810	0	0	0
T11	721628	0	0	0
T12	169822	0	0	0
T13	0	66045	0	0
T16	0	203212	0	0
T17	0	416371	0	0
T25	0	81935	0	0
T26	0	123902	0	0
T27	0	336277	0	0
T28	0	44391	0	0
T29	0	51484	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	151242	0	0
T13	279006	7106	0	0
T14	234167	0	0	0
T16	543036	0	0	0
T20	197270	0	0	0
T28	0	2633	0	0
T30	110277	0	0	0
T34	0	11195	0	0
T35	0	2853	0	0
T58	735159	0	0	0
T81	0	1194	0	0
T82	0	2483	0	0
T83	0	3028	0	0
T84	0	13595	0	0
T85	0	7680	0	0
T86	0	12421	0	0
T87	347809	0	0	0
T88	133037	0	0	0
T89	129284	0	0	0
T90	924741	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	133872	0	0
T13	279006	6234	0	0
T14	234167	0	0	0
T16	543036	0	0	0
T20	197270	0	0	0
T28	0	2325	0	0
T30	110277	0	0	0
T34	0	9776	0	0
T35	0	2351	0	0
T58	735159	0	0	0
T81	0	1052	0	0
T82	0	1995	0	0
T83	0	2785	0	0
T84	0	12210	0	0
T85	0	6490	0	0
T86	0	10855	0	0
T87	347809	0	0	0
T88	133037	0	0	0
T89	129284	0	0	0
T90	924741	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	149189	0	0
T13	279006	7294	0	0
T14	234167	0	0	0
T16	543036	0	0	0
T20	197270	0	0	0
T28	0	2563	0	0
T30	110277	0	0	0
T34	0	10526	0	0
T35	0	2723	0	0
T58	735159	0	0	0
T81	0	1258	0	0
T82	0	2582	0	0
T83	0	3113	0	0
T84	0	13331	0	0
T85	0	7852	0	0
T86	0	12096	0	0
T87	347809	0	0	0
T88	133037	0	0	0
T89	129284	0	0	0
T90	924741	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	149505	0	0
T13	279006	6988	0	0
T14	234167	0	0	0
T16	543036	0	0	0
T20	197270	0	0	0
T28	0	2488	0	0
T30	110277	0	0	0
T34	0	10902	0	0
T35	0	2827	0	0
T58	735159	0	0	0
T81	0	1242	0	0
T82	0	2279	0	0
T83	0	2979	0	0
T84	0	13245	0	0
T85	0	7608	0	0
T86	0	12487	0	0
T87	347809	0	0	0
T88	133037	0	0	0
T89	129284	0	0	0
T90	924741	0	0	0