Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9634440	0	0
ctrl_rd_A	2147483647	253425	0	0
intr_enable_rd_A	2147483647	225545	0	0
ovrd_rd_A	2147483647	252177	0	0
timeout_ctrl_rd_A	2147483647	251500	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9634440	0	0
T4	513735	160992	0	0
T5	235905	0	0	0
T6	286291	0	0	0
T7	39878	0	0	0
T8	127044	0	0	0
T9	183971	43751	0	0
T10	628767	0	0	0
T11	438836	0	0	0
T12	549298	0	0	0
T17	0	115365	0	0
T25	0	80825	0	0
T26	0	305540	0	0
T27	0	100455	0	0
T28	0	30379	0	0
T29	0	111827	0	0
T30	0	74185	0	0
T31	0	94825	0	0
T32	326607	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	253425	0	0
T9	183971	5551	0	0
T10	628767	0	0	0
T11	438836	0	0	0
T12	549298	0	0	0
T25	0	8906	0	0
T28	0	2951	0	0
T29	0	12499	0	0
T30	0	2152	0	0
T31	0	10793	0	0
T32	326607	0	0	0
T38	0	2739	0	0
T83	688428	0	0	0
T84	682259	0	0	0
T85	170104	0	0	0
T109	0	12468	0	0
T110	0	5782	0	0
T111	0	9097	0	0
T112	161661	0	0	0
T113	365907	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	225545	0	0
T9	183971	4516	0	0
T10	628767	0	0	0
T11	438836	0	0	0
T12	549298	0	0	0
T25	0	7605	0	0
T28	0	3003	0	0
T29	0	11477	0	0
T30	0	1912	0	0
T31	0	9799	0	0
T32	326607	0	0	0
T38	0	2295	0	0
T83	688428	0	0	0
T84	682259	0	0	0
T85	170104	0	0	0
T109	0	10766	0	0
T110	0	4917	0	0
T111	0	8095	0	0
T112	161661	0	0	0
T113	365907	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	252177	0	0
T9	183971	4948	0	0
T10	628767	0	0	0
T11	438836	0	0	0
T12	549298	0	0	0
T25	0	9419	0	0
T28	0	3194	0	0
T29	0	12247	0	0
T30	0	2071	0	0
T31	0	11123	0	0
T32	326607	0	0	0
T38	0	2587	0	0
T83	688428	0	0	0
T84	682259	0	0	0
T85	170104	0	0	0
T109	0	12147	0	0
T110	0	5536	0	0
T111	0	8824	0	0
T112	161661	0	0	0
T113	365907	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	251500	0	0
T9	183971	5099	0	0
T10	628767	0	0	0
T11	438836	0	0	0
T12	549298	0	0	0
T25	0	9205	0	0
T28	0	3281	0	0
T29	0	12067	0	0
T30	0	2024	0	0
T31	0	11250	0	0
T32	326607	0	0	0
T38	0	2743	0	0
T83	688428	0	0	0
T84	682259	0	0	0
T85	170104	0	0	0
T109	0	12458	0	0
T110	0	5373	0	0
T111	0	8931	0	0
T112	161661	0	0	0
T113	365907	0	0	0