Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71529806	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26617746

1

T1

48

T2

64

T3

347

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90040111	1			T1	10280		T2	4489		T3	3419
values[0x0]	3835939	1			T1	30		T2	50		T3	173
values[0x1]	4271502	1			T1	37		T2	39		T3	168

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49732436	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

48415116

1

T1

3407

T2

1579

T3

1433

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	438108	1			T1	30		T2	13		T3	15
valid_sources[0x01]	363728	1			T1	48		T2	20		T3	18
valid_sources[0x02]	423843	1			T1	40		T2	8		T3	22
valid_sources[0x03]	411070	1			T1	23		T2	1		T3	14
valid_sources[0x04]	374761	1			T1	42		T2	7		T3	12
valid_sources[0x05]	367613	1			T1	37		T2	20		T3	8
valid_sources[0x06]	349766	1			T1	45		T2	35		T3	8
valid_sources[0x07]	389209	1			T1	44		T2	18		T3	9
valid_sources[0x08]	370491	1			T1	34		T2	17		T3	19
valid_sources[0x09]	433517	1			T1	34		T2	25		T3	21
valid_sources[0x0a]	372681	1			T1	23		T2	15		T3	8
valid_sources[0x0b]	379372	1			T1	56		T2	44		T3	21
valid_sources[0x0c]	417304	1			T1	46		T2	2		T3	16
valid_sources[0x0d]	371416	1			T1	39		T2	15		T3	11
valid_sources[0x0e]	430514	1			T1	44		T2	12		T3	15
valid_sources[0x0f]	375881	1			T1	28		T2	35		T3	13
valid_sources[0x10]	430489	1			T1	38		T2	12		T3	9
valid_sources[0x11]	405095	1			T1	31		T2	13		T3	11
valid_sources[0x12]	358565	1			T1	42		T2	19		T3	15
valid_sources[0x13]	361993	1			T1	33		T2	34		T3	11
valid_sources[0x14]	374164	1			T1	45		T2	16		T3	6
valid_sources[0x15]	411186	1			T1	53		T2	17		T3	9
valid_sources[0x16]	380860	1			T1	49		T2	6		T3	11
valid_sources[0x17]	365556	1			T1	58		T2	24		T3	18
valid_sources[0x18]	370403	1			T1	33		T2	12		T3	21
valid_sources[0x19]	364034	1			T1	46		T2	12		T3	15
valid_sources[0x1a]	355479	1			T1	44		T2	14		T3	7
valid_sources[0x1b]	382964	1			T1	38		T2	21		T3	12
valid_sources[0x1c]	409283	1			T1	43		T2	6		T3	17
valid_sources[0x1d]	428921	1			T1	27		T2	4		T3	19
valid_sources[0x1e]	491194	1			T1	36		T2	15		T3	18
valid_sources[0x1f]	376719	1			T1	42		T2	7		T3	16
valid_sources[0x20]	375218	1			T1	47		T2	14		T3	14
valid_sources[0x21]	386529	1			T1	29		T2	15		T3	24
valid_sources[0x22]	434754	1			T1	40		T2	25		T3	11
valid_sources[0x23]	374679	1			T1	39		T2	20		T3	16
valid_sources[0x24]	406522	1			T1	32		T2	11		T3	18
valid_sources[0x25]	358105	1			T1	26		T2	12		T3	15
valid_sources[0x26]	355982	1			T1	44		T2	22		T3	17
valid_sources[0x27]	393826	1			T1	45		T2	25		T3	9
valid_sources[0x28]	394381	1			T1	35		T2	10		T3	7
valid_sources[0x29]	351946	1			T1	30		T2	31		T3	11
valid_sources[0x2a]	402243	1			T1	44		T2	23		T3	7
valid_sources[0x2b]	430624	1			T1	46		T2	3		T3	26
valid_sources[0x2c]	388072	1			T1	43		T2	21		T3	9
valid_sources[0x2d]	372074	1			T1	36		T2	2		T3	21
valid_sources[0x2e]	370014	1			T1	28		T2	10		T3	12
valid_sources[0x2f]	381497	1			T1	45		T2	23		T3	10
valid_sources[0x30]	379205	1			T1	35		T2	11		T3	14
valid_sources[0x31]	375122	1			T1	32		T2	8		T3	15
valid_sources[0x32]	419202	1			T1	31		T2	29		T3	3
valid_sources[0x33]	369179	1			T1	48		T2	14		T3	17
valid_sources[0x34]	390125	1			T1	60		T2	17		T3	22
valid_sources[0x35]	366220	1			T1	43		T2	17		T3	12
valid_sources[0x36]	450018	1			T1	35		T2	20		T3	28
valid_sources[0x37]	380970	1			T1	49		T2	30		T3	14
valid_sources[0x38]	367793	1			T1	48		T2	3		T3	8
valid_sources[0x39]	390531	1			T1	27		T2	16		T3	10
valid_sources[0x3a]	374476	1			T1	48		T2	21		T3	8
valid_sources[0x3b]	363389	1			T1	38		T2	19		T3	16
valid_sources[0x3c]	382414	1			T1	35		T2	20		T3	6
valid_sources[0x3d]	351171	1			T1	46		T2	55		T3	11
valid_sources[0x3e]	395028	1			T1	43		T2	17		T3	21
valid_sources[0x3f]	387426	1			T1	42		T2	4		T3	7
valid_sources[0x40]	446066	1			T1	40		T2	29		T3	22
valid_sources[0x41]	349286	1			T1	38		T2	7		T3	15
valid_sources[0x42]	461531	1			T1	29		T2	29		T3	8
valid_sources[0x43]	371978	1			T1	41		T2	12		T3	13
valid_sources[0x44]	452519	1			T1	51		T2	3		T3	21
valid_sources[0x45]	360898	1			T1	48		T2	13		T3	18
valid_sources[0x46]	374332	1			T1	60		T2	13		T3	24
valid_sources[0x47]	384740	1			T1	42		T2	3		T3	12
valid_sources[0x48]	366802	1			T1	47		T2	12		T3	15
valid_sources[0x49]	368179	1			T1	51		T2	18		T3	18
valid_sources[0x4a]	391129	1			T1	44		T2	6		T3	13
valid_sources[0x4b]	371031	1			T1	30		T2	15		T3	8
valid_sources[0x4c]	377121	1			T1	29		T2	24		T3	25
valid_sources[0x4d]	355558	1			T1	20		T2	18		T3	15
valid_sources[0x4e]	398875	1			T1	50		T2	24		T3	17
valid_sources[0x4f]	373432	1			T1	29		T2	22		T3	13
valid_sources[0x50]	363163	1			T1	30		T2	9		T3	19
valid_sources[0x51]	395652	1			T1	46		T2	11		T3	10
valid_sources[0x52]	371439	1			T1	25		T2	18		T3	10
valid_sources[0x53]	378201	1			T1	34		T2	14		T3	6
valid_sources[0x54]	360970	1			T1	44		T2	16		T3	14
valid_sources[0x55]	397146	1			T1	48		T2	2		T3	17
valid_sources[0x56]	403529	1			T1	29		T2	19		T3	12
valid_sources[0x57]	351337	1			T1	52		T2	32		T3	18
valid_sources[0x58]	383864	1			T1	43		T2	11		T3	11
valid_sources[0x59]	367840	1			T1	33		T2	32		T3	14
valid_sources[0x5a]	486563	1			T1	40		T2	15		T3	10
valid_sources[0x5b]	355537	1			T1	36		T2	19		T3	3
valid_sources[0x5c]	339377	1			T1	30		T2	12		T3	16
valid_sources[0x5d]	375915	1			T1	39		T2	16		T3	20
valid_sources[0x5e]	400756	1			T1	43		T2	10		T3	14
valid_sources[0x5f]	367221	1			T1	51		T2	14		T3	11
valid_sources[0x60]	391609	1			T1	39		T2	14		T3	13
valid_sources[0x61]	361583	1			T1	39		T2	31		T3	21
valid_sources[0x62]	372428	1			T1	40		T2	7		T3	15
valid_sources[0x63]	363956	1			T1	37		T2	14		T3	20
valid_sources[0x64]	395227	1			T1	55		T2	22		T3	29
valid_sources[0x65]	365716	1			T1	47		T2	9		T3	19
valid_sources[0x66]	359111	1			T1	37		T2	33		T3	8
valid_sources[0x67]	391105	1			T1	36		T2	4		T3	12
valid_sources[0x68]	345701	1			T1	40		T2	45		T3	24
valid_sources[0x69]	384634	1			T1	33		T2	23		T3	19
valid_sources[0x6a]	366086	1			T1	33		T2	2		T3	12
valid_sources[0x6b]	391573	1			T1	28		T2	18		T3	14
valid_sources[0x6c]	397157	1			T1	37		T2	24		T3	12
valid_sources[0x6d]	367462	1			T1	37		T2	17		T3	16
valid_sources[0x6e]	409214	1			T1	44		T2	22		T3	13
valid_sources[0x6f]	356673	1			T1	25		T2	5		T3	18
valid_sources[0x70]	367334	1			T1	34		T2	16		T3	15
valid_sources[0x71]	390632	1			T1	56		T2	20		T3	10
valid_sources[0x72]	362369	1			T1	30		T2	12		T3	21
valid_sources[0x73]	371355	1			T1	39		T2	28		T3	15
valid_sources[0x74]	390966	1			T1	56		T2	8		T3	18
valid_sources[0x75]	371952	1			T1	46		T2	31		T3	17
valid_sources[0x76]	395925	1			T1	64		T2	11		T3	17
valid_sources[0x77]	390836	1			T1	34		T2	3		T3	12
valid_sources[0x78]	372957	1			T1	41		T2	13		T3	14
valid_sources[0x79]	424792	1			T1	40		T2	23		T3	10
valid_sources[0x7a]	406960	1			T1	64		T2	8		T3	12
valid_sources[0x7b]	372250	1			T1	35		T2	21		T3	8
valid_sources[0x7c]	361133	1			T1	33		T2	17		T3	20
valid_sources[0x7d]	350438	1			T1	45		T2	1		T3	7
valid_sources[0x7e]	368512	1			T1	39		T2	28		T3	27
valid_sources[0x7f]	383641	1			T1	37		T2	26		T3	7
valid_sources[0x80]	367717	1			T1	38		T2	12		T3	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19510333

1

T1

2

T2

5

T3

232

values[0x0]

all_enables

biggest_size

3583852

1

T1

23

T2

34

T3

71

values[0x1]

all_enables

biggest_size

3523561

1

T1

23

T2

25

T3

44