Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	11662995	0	0
ctrl_rd_A	2147483647	222686	0	0
intr_enable_rd_A	2147483647	198502	0	0
ovrd_rd_A	2147483647	221299	0	0
timeout_ctrl_rd_A	2147483647	223135	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11662995	0	0
T16	533475	167692	0	0
T21	162036	0	0	0
T27	181051	35172	0	0
T28	0	193060	0	0
T33	408447	0	0	0
T40	0	79937	0	0
T41	0	225044	0	0
T42	0	40185	0	0
T43	0	147201	0	0
T44	0	177761	0	0
T45	0	37257	0	0
T46	0	105072	0	0
T47	253965	0	0	0
T48	464274	0	0	0
T49	13826	0	0	0
T50	23051	0	0	0
T51	405994	0	0	0
T52	137011	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	222686	0	0
T16	533475	9051	0	0
T21	162036	0	0	0
T27	181051	0	0	0
T33	408447	0	0	0
T43	0	16652	0	0
T45	0	1783	0	0
T47	253965	0	0	0
T48	464274	0	0	0
T49	13826	0	0	0
T50	23051	0	0	0
T51	405994	0	0	0
T52	137011	0	0	0
T66	0	4232	0	0
T68	0	6676	0	0
T117	0	5363	0	0
T118	0	17304	0	0
T119	0	9161	0	0
T120	0	9730	0	0
T121	0	18754	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	198502	0	0
T16	533475	8045	0	0
T21	162036	0	0	0
T27	181051	0	0	0
T33	408447	0	0	0
T43	0	14799	0	0
T45	0	1641	0	0
T47	253965	0	0	0
T48	464274	0	0	0
T49	13826	0	0	0
T50	23051	0	0	0
T51	405994	0	0	0
T52	137011	0	0	0
T66	0	3601	0	0
T94	0	31	0	0
T95	0	9	0	0
T117	0	4943	0	0
T118	0	15609	0	0
T119	0	8152	0	0
T122	0	9	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	221299	0	0
T16	533475	9387	0	0
T21	162036	0	0	0
T27	181051	0	0	0
T33	408447	0	0	0
T43	0	16467	0	0
T45	0	1865	0	0
T47	253965	0	0	0
T48	464274	0	0	0
T49	13826	0	0	0
T50	23051	0	0	0
T51	405994	0	0	0
T52	137011	0	0	0
T66	0	4343	0	0
T68	0	6612	0	0
T117	0	5342	0	0
T118	0	17405	0	0
T119	0	9006	0	0
T120	0	9183	0	0
T121	0	19359	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	223135	0	0
T16	533475	8991	0	0
T21	162036	0	0	0
T27	181051	0	0	0
T33	408447	0	0	0
T43	0	16937	0	0
T45	0	1839	0	0
T47	253965	0	0	0
T48	464274	0	0	0
T49	13826	0	0	0
T50	23051	0	0	0
T51	405994	0	0	0
T52	137011	0	0	0
T66	0	3940	0	0
T68	0	7093	0	0
T117	0	5339	0	0
T118	0	17618	0	0
T119	0	9309	0	0
T120	0	9463	0	0
T121	0	19625	0	0