Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65725176	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23796632

1

T1

31

T2

213

T3

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82853343	1			T1	25		T2	4748		T3	23559
values[0x0]	3158611	1			T1	30		T2	166		T3	43
values[0x1]	3509854	1			T1	24		T2	168		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45666706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

43855102

1

T1

38

T2

1791

T3

11915

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	324386	1			T2	13		T3	73		T5	55
valid_sources[0x01]	351056	1			T2	5		T3	102		T5	67
valid_sources[0x02]	362486	1			T2	16		T3	174		T5	60
valid_sources[0x03]	338497	1			T2	17		T3	70		T5	55
valid_sources[0x04]	327380	1			T2	31		T3	102		T5	69
valid_sources[0x05]	337990	1			T2	11		T3	81		T5	67
valid_sources[0x06]	316855	1			T2	3		T3	94		T5	53
valid_sources[0x07]	323947	1			T2	2		T3	143		T5	54
valid_sources[0x08]	350034	1			T2	17		T3	82		T5	49
valid_sources[0x09]	345084	1			T2	15		T3	80		T5	68
valid_sources[0x0a]	336403	1			T1	79		T2	15		T3	106
valid_sources[0x0b]	339329	1			T2	7		T3	87		T5	65
valid_sources[0x0c]	374614	1			T2	36		T3	108		T5	61
valid_sources[0x0d]	348273	1			T2	23		T3	122		T5	52
valid_sources[0x0e]	327933	1			T2	7		T3	116		T5	47
valid_sources[0x0f]	345496	1			T2	19		T3	96		T5	53
valid_sources[0x10]	356674	1			T2	10		T3	82		T5	54
valid_sources[0x11]	341777	1			T2	21		T3	41		T5	44
valid_sources[0x12]	403606	1			T2	23		T3	79		T5	46
valid_sources[0x13]	414506	1			T2	43		T3	94		T5	64
valid_sources[0x14]	361241	1			T2	2		T3	71		T5	67
valid_sources[0x15]	354809	1			T2	18		T3	113		T5	63
valid_sources[0x16]	379884	1			T2	11		T3	103		T5	63
valid_sources[0x17]	335437	1			T2	25		T3	136		T5	62
valid_sources[0x18]	367524	1			T2	24		T3	93		T5	44
valid_sources[0x19]	355478	1			T2	65		T3	76		T5	46
valid_sources[0x1a]	387873	1			T2	24		T3	89		T5	57
valid_sources[0x1b]	341287	1			T2	19		T3	57		T5	51
valid_sources[0x1c]	342045	1			T2	34		T3	97		T5	55
valid_sources[0x1d]	341328	1			T2	7		T3	64		T5	58
valid_sources[0x1e]	360148	1			T2	35		T3	99		T5	40
valid_sources[0x1f]	373448	1			T2	29		T3	53		T5	95
valid_sources[0x20]	371838	1			T2	10		T3	107		T5	53
valid_sources[0x21]	361164	1			T2	29		T3	112		T5	90
valid_sources[0x22]	373430	1			T2	2		T3	126		T5	57
valid_sources[0x23]	407908	1			T2	29		T3	28		T5	63
valid_sources[0x24]	328555	1			T2	20		T3	68		T5	72
valid_sources[0x25]	344150	1			T2	61		T3	94		T5	57
valid_sources[0x26]	322778	1			T2	15		T3	84		T5	45
valid_sources[0x27]	359045	1			T2	18		T3	113		T5	70
valid_sources[0x28]	353367	1			T2	30		T3	92		T5	41
valid_sources[0x29]	332191	1			T2	6		T3	130		T5	84
valid_sources[0x2a]	339702	1			T2	16		T3	136		T5	50
valid_sources[0x2b]	350030	1			T2	15		T3	56		T5	48
valid_sources[0x2c]	337182	1			T2	46		T3	109		T5	67
valid_sources[0x2d]	341972	1			T2	22		T3	53		T5	53
valid_sources[0x2e]	322600	1			T2	20		T3	113		T5	48
valid_sources[0x2f]	333466	1			T2	5		T3	83		T5	58
valid_sources[0x30]	406897	1			T2	16		T3	83		T5	42
valid_sources[0x31]	366993	1			T2	28		T3	95		T5	62
valid_sources[0x32]	339456	1			T2	1		T3	106		T5	66
valid_sources[0x33]	436407	1			T2	7		T3	93		T5	44
valid_sources[0x34]	344592	1			T2	4		T3	99		T5	80
valid_sources[0x35]	333354	1			T2	21		T3	97		T5	57
valid_sources[0x36]	355907	1			T2	18		T3	100		T5	51
valid_sources[0x37]	342921	1			T2	22		T3	100		T5	72
valid_sources[0x38]	345376	1			T2	18		T3	108		T5	41
valid_sources[0x39]	349269	1			T2	15		T3	119		T5	51
valid_sources[0x3a]	369288	1			T2	27		T3	112		T5	53
valid_sources[0x3b]	323922	1			T2	26		T3	83		T5	42
valid_sources[0x3c]	326228	1			T2	24		T3	106		T5	84
valid_sources[0x3d]	419171	1			T2	27		T3	78		T5	73
valid_sources[0x3e]	372276	1			T2	19		T3	72		T5	71
valid_sources[0x3f]	378919	1			T2	28		T3	78		T5	54
valid_sources[0x40]	384685	1			T2	7		T3	86		T5	60
valid_sources[0x41]	381347	1			T2	15		T3	89		T5	77
valid_sources[0x42]	498884	1			T2	47		T3	104		T5	60
valid_sources[0x43]	347034	1			T2	17		T3	121		T5	60
valid_sources[0x44]	328564	1			T2	22		T3	95		T5	45
valid_sources[0x45]	346188	1			T2	19		T3	102		T5	47
valid_sources[0x46]	377948	1			T2	11		T3	83		T5	36
valid_sources[0x47]	354420	1			T2	22		T3	101		T5	74
valid_sources[0x48]	314605	1			T2	9		T3	66		T5	37
valid_sources[0x49]	320624	1			T2	8		T3	107		T5	58
valid_sources[0x4a]	331111	1			T2	11		T3	83		T5	56
valid_sources[0x4b]	322592	1			T2	11		T3	93		T5	61
valid_sources[0x4c]	328909	1			T2	32		T3	87		T5	53
valid_sources[0x4d]	368163	1			T2	30		T3	96		T5	34
valid_sources[0x4e]	314219	1			T2	32		T3	121		T5	47
valid_sources[0x4f]	363331	1			T2	39		T3	120		T5	31
valid_sources[0x50]	398615	1			T2	16		T3	81		T5	56
valid_sources[0x51]	332494	1			T2	29		T3	114		T5	39
valid_sources[0x52]	357822	1			T2	19		T3	73		T5	38
valid_sources[0x53]	317504	1			T2	19		T3	102		T5	62
valid_sources[0x54]	342664	1			T2	17		T3	90		T5	38
valid_sources[0x55]	320130	1			T2	56		T3	98		T5	44
valid_sources[0x56]	313346	1			T2	1		T3	96		T5	49
valid_sources[0x57]	330075	1			T2	18		T3	123		T5	54
valid_sources[0x58]	385959	1			T2	1		T3	93		T5	57
valid_sources[0x59]	376639	1			T2	28		T3	118		T5	59
valid_sources[0x5a]	326269	1			T2	14		T3	75		T5	59
valid_sources[0x5b]	338731	1			T2	18		T3	75		T5	76
valid_sources[0x5c]	347928	1			T2	46		T3	50		T5	70
valid_sources[0x5d]	378547	1			T2	17		T3	70		T5	76
valid_sources[0x5e]	334825	1			T2	33		T3	90		T5	56
valid_sources[0x5f]	329441	1			T2	41		T3	67		T5	49
valid_sources[0x60]	386997	1			T2	19		T3	114		T5	79
valid_sources[0x61]	337199	1			T2	13		T3	81		T5	52
valid_sources[0x62]	351347	1			T2	13		T3	93		T5	57
valid_sources[0x63]	345919	1			T2	16		T3	99		T5	36
valid_sources[0x64]	360324	1			T2	7		T3	40		T5	60
valid_sources[0x65]	328697	1			T2	18		T3	79		T5	86
valid_sources[0x66]	430629	1			T2	22		T3	135		T5	63
valid_sources[0x67]	332505	1			T2	6		T3	91		T5	71
valid_sources[0x68]	343597	1			T2	28		T3	105		T5	61
valid_sources[0x69]	341808	1			T3	111		T5	96		T6	75
valid_sources[0x6a]	318769	1			T2	15		T3	81		T5	74
valid_sources[0x6b]	328775	1			T2	49		T3	89		T5	66
valid_sources[0x6c]	347597	1			T2	11		T3	107		T5	65
valid_sources[0x6d]	330977	1			T2	24		T3	74		T5	67
valid_sources[0x6e]	319155	1			T2	21		T3	86		T5	51
valid_sources[0x6f]	356090	1			T2	37		T3	94		T5	82
valid_sources[0x70]	346426	1			T2	17		T3	107		T5	88
valid_sources[0x71]	327123	1			T2	11		T3	89		T5	50
valid_sources[0x72]	339891	1			T2	8		T3	88		T5	48
valid_sources[0x73]	324175	1			T2	7		T3	93		T5	48
valid_sources[0x74]	383494	1			T2	9		T3	95		T5	49
valid_sources[0x75]	369840	1			T2	45		T3	79		T4	45
valid_sources[0x76]	364072	1			T2	9		T3	92		T5	53
valid_sources[0x77]	345115	1			T2	28		T3	97		T5	73
valid_sources[0x78]	393569	1			T2	38		T3	102		T5	63
valid_sources[0x79]	339857	1			T2	6		T3	78		T5	62
valid_sources[0x7a]	335712	1			T2	13		T3	100		T5	62
valid_sources[0x7b]	338233	1			T2	5		T3	107		T5	43
valid_sources[0x7c]	334295	1			T2	14		T3	112		T5	61
valid_sources[0x7d]	319131	1			T2	14		T3	64		T5	60
valid_sources[0x7e]	353388	1			T2	11		T3	119		T5	43
valid_sources[0x7f]	393440	1			T2	3		T3	105		T5	53
valid_sources[0x80]	333388	1			T2	23		T3	80		T5	58

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17979540

1

T1

13

T2

113

T4

6

values[0x0]

all_enables

biggest_size

2937591

1

T1

12

T2

66

T3

30

values[0x1]

all_enables

biggest_size

2879501

1

T1

6

T2

34

T3

26