Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9610534	0	0
ctrl_rd_A	2147483647	146486	0	0
intr_enable_rd_A	2147483647	131947	0	0
ovrd_rd_A	2147483647	146138	0	0
timeout_ctrl_rd_A	2147483647	145778	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9610534	0	0
T21	350662	0	0	0
T25	0	34894	0	0
T27	162195	66345	0	0
T28	0	197873	0	0
T35	0	160076	0	0
T36	0	207984	0	0
T37	0	109876	0	0
T38	0	164670	0	0
T39	0	53901	0	0
T40	0	339748	0	0
T41	0	8153	0	0
T42	571405	0	0	0
T43	602306	0	0	0
T44	256054	0	0	0
T45	546553	0	0	0
T46	682462	0	0	0
T47	33819	0	0	0
T48	198249	0	0	0
T49	842304	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	146486	0	0
T25	108633	1710	0	0
T37	0	4854	0	0
T59	236753	0	0	0
T91	0	4747	0	0
T127	0	2931	0	0
T128	0	5602	0	0
T129	0	15350	0	0
T130	0	14463	0	0
T131	0	14071	0	0
T132	0	9495	0	0
T133	0	14999	0	0
T134	660076	0	0	0
T135	674456	0	0	0
T136	416675	0	0	0
T137	443821	0	0	0
T138	241945	0	0	0
T139	29093	0	0	0
T140	163542	0	0	0
T141	82175	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	131947	0	0
T25	108633	1565	0	0
T37	0	4306	0	0
T59	236753	0	0	0
T91	0	4535	0	0
T127	0	2759	0	0
T128	0	5342	0	0
T129	0	13943	0	0
T130	0	12557	0	0
T134	660076	0	0	0
T135	674456	0	0	0
T136	416675	0	0	0
T137	443821	0	0	0
T138	241945	0	0	0
T139	29093	0	0	0
T140	163542	0	0	0
T141	82175	0	0	0
T142	0	5	0	0
T143	0	19	0	0
T144	0	36	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	146138	0	0
T25	108633	1858	0	0
T37	0	5003	0	0
T59	236753	0	0	0
T91	0	4972	0	0
T127	0	2848	0	0
T128	0	6015	0	0
T129	0	15457	0	0
T130	0	14578	0	0
T131	0	14375	0	0
T132	0	9531	0	0
T133	0	15043	0	0
T134	660076	0	0	0
T135	674456	0	0	0
T136	416675	0	0	0
T137	443821	0	0	0
T138	241945	0	0	0
T139	29093	0	0	0
T140	163542	0	0	0
T141	82175	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	145778	0	0
T25	108633	1775	0	0
T37	0	4894	0	0
T59	236753	0	0	0
T91	0	4805	0	0
T127	0	2966	0	0
T128	0	5669	0	0
T129	0	15459	0	0
T130	0	14831	0	0
T131	0	14000	0	0
T132	0	9499	0	0
T133	0	15153	0	0
T134	660076	0	0	0
T135	674456	0	0	0
T136	416675	0	0	0
T137	443821	0	0	0
T138	241945	0	0	0
T139	29093	0	0	0
T140	163542	0	0	0
T141	82175	0	0	0