Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 60292170 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 23289630 1 T1 93845 T2 9 T3 132



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 76890021 1 T1 271734 T2 1653 T3 331
values[0x0] 3167783 1 T1 373 T2 7 T3 66
values[0x1] 3523996 1 T1 382 T2 6 T3 50



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 42016983 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 41564817 1 T1 140778 T2 546 T3 206



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 310228 1 T1 3537 T2 6 T4 328
valid_sources[0x01] 316602 1 T1 1387 T2 7 T4 317
valid_sources[0x02] 358279 1 T2 5 T4 316 T6 54
valid_sources[0x03] 313036 1 T1 357 T2 10 T4 334
valid_sources[0x04] 298251 1 T1 1276 T2 11 T4 289
valid_sources[0x05] 313594 1 T1 4216 T2 10 T4 324
valid_sources[0x06] 310370 1 T1 94 T2 6 T4 316
valid_sources[0x07] 320494 1 T1 24 T2 8 T4 335
valid_sources[0x08] 341406 1 T1 1084 T2 3 T4 354
valid_sources[0x09] 293214 1 T1 2 T2 6 T4 294
valid_sources[0x0a] 348545 1 T1 1 T2 4 T4 287
valid_sources[0x0b] 323494 1 T2 16 T4 301 T6 95
valid_sources[0x0c] 350797 1 T1 1 T2 5 T4 319
valid_sources[0x0d] 334496 1 T2 6 T4 291 T6 56
valid_sources[0x0e] 322499 1 T1 45 T2 3 T4 346
valid_sources[0x0f] 315319 1 T1 14 T2 5 T4 265
valid_sources[0x10] 309518 1 T1 9406 T2 2 T4 350
valid_sources[0x11] 314485 1 T1 270 T2 12 T4 280
valid_sources[0x12] 288131 1 T1 26 T2 6 T4 309
valid_sources[0x13] 300579 1 T1 2105 T2 9 T4 319
valid_sources[0x14] 323962 1 T1 3 T2 4 T4 341
valid_sources[0x15] 300190 1 T1 98 T2 7 T4 338
valid_sources[0x16] 348316 1 T1 4647 T2 8 T4 323
valid_sources[0x17] 340356 1 T2 6 T4 277 T6 112
valid_sources[0x18] 324155 1 T1 2162 T2 5 T4 332
valid_sources[0x19] 304442 1 T1 4807 T2 5 T4 338
valid_sources[0x1a] 321082 1 T1 531 T2 5 T4 322
valid_sources[0x1b] 342726 1 T1 493 T2 7 T4 315
valid_sources[0x1c] 348123 1 T1 1640 T2 11 T4 366
valid_sources[0x1d] 381018 1 T1 348 T2 5 T4 342
valid_sources[0x1e] 315827 1 T2 4 T4 309 T6 127
valid_sources[0x1f] 311963 1 T1 110 T2 7 T4 356
valid_sources[0x20] 326507 1 T1 4802 T2 6 T4 348
valid_sources[0x21] 302357 1 T1 3341 T2 5 T4 322
valid_sources[0x22] 333115 1 T2 3 T4 328 T6 6
valid_sources[0x23] 295093 1 T1 51 T2 16 T4 373
valid_sources[0x24] 336890 1 T1 1 T2 3 T4 284
valid_sources[0x25] 318219 1 T1 2 T2 8 T4 305
valid_sources[0x26] 313053 1 T1 5 T2 9 T4 315
valid_sources[0x27] 329054 1 T1 3 T2 5 T4 305
valid_sources[0x28] 310091 1 T1 2 T2 1 T4 297
valid_sources[0x29] 435659 1 T1 2438 T2 5 T4 319
valid_sources[0x2a] 304160 1 T1 109 T2 9 T4 296
valid_sources[0x2b] 298201 1 T1 3 T2 8 T4 394
valid_sources[0x2c] 325647 1 T1 112 T2 9 T4 280
valid_sources[0x2d] 321638 1 T1 4 T2 7 T4 339
valid_sources[0x2e] 296311 1 T2 5 T4 310 T6 42
valid_sources[0x2f] 344444 1 T1 1 T2 10 T4 271
valid_sources[0x30] 292757 1 T2 4 T4 304 T6 126
valid_sources[0x31] 330048 1 T1 6373 T2 8 T4 304
valid_sources[0x32] 300679 1 T1 41 T2 11 T4 310
valid_sources[0x33] 339332 1 T1 33 T2 13 T4 315
valid_sources[0x34] 299894 1 T1 5579 T2 10 T4 321
valid_sources[0x35] 607068 1 T1 2 T2 11 T4 295
valid_sources[0x36] 306478 1 T1 60 T2 8 T4 291
valid_sources[0x37] 374858 1 T1 2 T2 2 T4 287
valid_sources[0x38] 328671 1 T1 31 T2 5 T4 337
valid_sources[0x39] 312569 1 T1 1421 T2 4 T4 335
valid_sources[0x3a] 325090 1 T1 7103 T2 4 T4 308
valid_sources[0x3b] 342714 1 T1 7813 T2 7 T4 311
valid_sources[0x3c] 309134 1 T1 1067 T2 4 T4 307
valid_sources[0x3d] 329578 1 T1 906 T2 10 T4 298
valid_sources[0x3e] 287592 1 T2 9 T4 339 T6 84
valid_sources[0x3f] 354935 1 T1 27 T2 3 T4 272
valid_sources[0x40] 302212 1 T1 18 T2 6 T4 289
valid_sources[0x41] 336380 1 T1 3 T2 8 T4 296
valid_sources[0x42] 327773 1 T1 487 T2 8 T4 310
valid_sources[0x43] 356566 1 T1 24 T2 4 T4 316
valid_sources[0x44] 329353 1 T1 1 T2 4 T4 364
valid_sources[0x45] 332559 1 T1 2 T2 2 T4 338
valid_sources[0x46] 327034 1 T1 1349 T2 4 T4 270
valid_sources[0x47] 296035 1 T1 663 T2 3 T4 280
valid_sources[0x48] 330361 1 T1 32 T2 7 T3 1
valid_sources[0x49] 328616 1 T1 7683 T2 4 T4 317
valid_sources[0x4a] 357931 1 T1 1527 T2 1 T4 334
valid_sources[0x4b] 298527 1 T1 2 T2 6 T4 389
valid_sources[0x4c] 303090 1 T1 45 T2 2 T4 332
valid_sources[0x4d] 321145 1 T1 3086 T2 14 T4 378
valid_sources[0x4e] 303869 1 T1 3946 T2 2 T4 287
valid_sources[0x4f] 297769 1 T1 4476 T2 4 T4 388
valid_sources[0x50] 355421 1 T1 23 T2 5 T4 281
valid_sources[0x51] 298905 1 T1 2520 T2 12 T4 333
valid_sources[0x52] 327606 1 T2 4 T4 366 T6 83
valid_sources[0x53] 344215 1 T1 3140 T2 5 T4 317
valid_sources[0x54] 337155 1 T1 4 T2 3 T4 369
valid_sources[0x55] 304210 1 T1 134 T2 1 T4 338
valid_sources[0x56] 310351 1 T1 54 T2 3 T4 352
valid_sources[0x57] 313573 1 T1 106 T2 7 T4 358
valid_sources[0x58] 329527 1 T1 10516 T2 4 T4 295
valid_sources[0x59] 308641 1 T1 542 T2 7 T4 318
valid_sources[0x5a] 311870 1 T1 154 T2 9 T4 345
valid_sources[0x5b] 416244 1 T1 39 T2 3 T4 275
valid_sources[0x5c] 315809 1 T2 7 T4 275 T6 114
valid_sources[0x5d] 312709 1 T1 649 T2 10 T4 370
valid_sources[0x5e] 307546 1 T1 3 T2 15 T4 339
valid_sources[0x5f] 304920 1 T1 3 T2 11 T4 289
valid_sources[0x60] 350201 1 T1 3349 T2 4 T4 295
valid_sources[0x61] 316611 1 T1 1 T2 7 T4 297
valid_sources[0x62] 301893 1 T1 594 T2 5 T4 324
valid_sources[0x63] 407978 1 T2 6 T4 361 T6 77
valid_sources[0x64] 358888 1 T1 42 T2 5 T4 359
valid_sources[0x65] 377351 1 T1 35 T2 12 T4 284
valid_sources[0x66] 333700 1 T1 32 T2 2 T4 266
valid_sources[0x67] 317720 1 T1 2 T2 12 T4 311
valid_sources[0x68] 342337 1 T1 403 T2 4 T4 294
valid_sources[0x69] 300918 1 T2 10 T4 347 T6 23
valid_sources[0x6a] 314347 1 T1 2904 T2 6 T4 326
valid_sources[0x6b] 299564 1 T1 214 T2 9 T4 301
valid_sources[0x6c] 308242 1 T1 4 T2 4 T4 341
valid_sources[0x6d] 384902 1 T1 9211 T2 3 T4 343
valid_sources[0x6e] 390990 1 T1 2 T2 16 T4 346
valid_sources[0x6f] 421917 1 T2 9 T4 285 T6 61
valid_sources[0x70] 336117 1 T2 7 T4 340 T6 99
valid_sources[0x71] 300079 1 T1 1648 T2 4 T4 337
valid_sources[0x72] 329450 1 T1 126 T2 9 T4 322
valid_sources[0x73] 302284 1 T1 32 T2 3 T4 341
valid_sources[0x74] 350463 1 T1 4490 T2 5 T4 366
valid_sources[0x75] 284158 1 T2 11 T4 269 T6 76
valid_sources[0x76] 310055 1 T1 1011 T2 4 T4 275
valid_sources[0x77] 322184 1 T1 1 T2 4 T4 248
valid_sources[0x78] 336736 1 T1 10 T2 1 T4 307
valid_sources[0x79] 312553 1 T1 95 T2 7 T4 289
valid_sources[0x7a] 307544 1 T1 4 T2 12 T4 298
valid_sources[0x7b] 360327 1 T2 8 T4 342 T6 72
valid_sources[0x7c] 314628 1 T4 334 T6 119 T7 233
valid_sources[0x7d] 322177 1 T2 5 T4 357 T6 28
valid_sources[0x7e] 294965 1 T1 130 T2 8 T4 318
valid_sources[0x7f] 335425 1 T1 1 T2 4 T4 349
valid_sources[0x80] 311680 1 T2 2 T4 364 T6 51



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 17448562 1 T1 93585 T2 3 T3 86
values[0x0] all_enables biggest_size 2947292 1 T1 166 T2 3 T3 32
values[0x1] all_enables biggest_size 2893776 1 T1 94 T2 3 T3 14

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%