Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9517165	0	0
ctrl_rd_A	2147483647	187356	0	0
intr_enable_rd_A	2147483647	166985	0	0
ovrd_rd_A	2147483647	183026	0	0
timeout_ctrl_rd_A	2147483647	184606	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9517165	0	0
T4	181820	72954	0	0
T5	41371	0	0	0
T6	387309	0	0	0
T7	287213	0	0	0
T8	1254	0	0	0
T9	156780	0	0	0
T10	131890	0	0	0
T11	208775	0	0	0
T12	586920	0	0	0
T15	0	123535	0	0
T17	590152	0	0	0
T18	0	136545	0	0
T28	0	93982	0	0
T29	0	58804	0	0
T30	0	78060	0	0
T31	0	84235	0	0
T32	0	290834	0	0
T33	0	234168	0	0
T34	0	73644	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	187356	0	0
T27	3031	0	0	0
T28	385761	9198	0	0
T29	224077	4273	0	0
T30	0	5318	0	0
T31	0	9724	0	0
T34	0	8386	0	0
T80	0	3143	0	0
T81	0	22578	0	0
T82	0	11651	0	0
T83	0	12258	0	0
T84	0	9674	0	0
T85	211028	0	0	0
T86	293916	0	0	0
T87	109096	0	0	0
T88	119404	0	0	0
T89	489354	0	0	0
T90	179880	0	0	0
T91	270415	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	166985	0	0
T27	3031	0	0	0
T28	385761	8261	0	0
T29	224077	4041	0	0
T30	0	4630	0	0
T31	0	8830	0	0
T34	0	7640	0	0
T80	0	2832	0	0
T81	0	19285	0	0
T82	0	10086	0	0
T83	0	10432	0	0
T85	211028	0	0	0
T86	293916	0	0	0
T87	109096	0	0	0
T88	119404	0	0	0
T89	489354	0	0	0
T90	179880	0	0	0
T91	270415	0	0	0
T92	0	19	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	183026	0	0
T27	3031	0	0	0
T28	385761	9599	0	0
T29	224077	4233	0	0
T30	0	5643	0	0
T31	0	9133	0	0
T34	0	7908	0	0
T80	0	3133	0	0
T81	0	21732	0	0
T82	0	11859	0	0
T83	0	11434	0	0
T84	0	9277	0	0
T85	211028	0	0	0
T86	293916	0	0	0
T87	109096	0	0	0
T88	119404	0	0	0
T89	489354	0	0	0
T90	179880	0	0	0
T91	270415	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	184606	0	0
T27	3031	0	0	0
T28	385761	9488	0	0
T29	224077	4439	0	0
T30	0	5130	0	0
T31	0	9900	0	0
T34	0	8381	0	0
T80	0	2970	0	0
T81	0	21955	0	0
T82	0	11161	0	0
T83	0	11549	0	0
T84	0	9931	0	0
T85	211028	0	0	0
T86	293916	0	0	0
T87	109096	0	0	0
T88	119404	0	0	0
T89	489354	0	0	0
T90	179880	0	0	0
T91	270415	0	0	0