Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64049622	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24609599

1

T1

468

T2

168

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	81105480	1			T1	3435		T2	8577		T3	11471
values[0x0]	3572343	1			T1	195		T2	191		T3	8
values[0x1]	3981398	1			T1	203		T2	187		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44542206	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

44117015

1

T1

1491

T2

2966

T3

3876

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	343410	1			T1	3		T2	25		T3	46
valid_sources[0x01]	327871	1			T1	14		T2	41		T3	64
valid_sources[0x02]	370323	1			T1	13		T2	83		T3	51
valid_sources[0x03]	341221	1			T1	14		T2	31		T3	41
valid_sources[0x04]	349913	1			T1	11		T2	69		T3	40
valid_sources[0x05]	315332	1			T1	13		T2	53		T3	41
valid_sources[0x06]	340077	1			T1	17		T2	48		T3	55
valid_sources[0x07]	334233	1			T1	10		T2	67		T3	37
valid_sources[0x08]	312794	1			T1	28		T2	57		T3	49
valid_sources[0x09]	373694	1			T1	16		T2	25		T3	42
valid_sources[0x0a]	322161	1			T1	25		T2	38		T3	39
valid_sources[0x0b]	364821	1			T1	21		T2	25		T3	51
valid_sources[0x0c]	337000	1			T1	9		T2	24		T3	55
valid_sources[0x0d]	354367	1			T1	15		T2	42		T3	54
valid_sources[0x0e]	307073	1			T1	14		T2	32		T3	35
valid_sources[0x0f]	338132	1			T1	33		T2	36		T3	35
valid_sources[0x10]	384280	1			T1	7		T2	71		T3	36
valid_sources[0x11]	320162	1			T1	18		T2	13		T3	39
valid_sources[0x12]	325625	1			T1	12		T2	35		T3	59
valid_sources[0x13]	353689	1			T1	14		T2	35		T3	43
valid_sources[0x14]	403253	1			T1	23		T2	33		T3	44
valid_sources[0x15]	372849	1			T1	5		T2	34		T3	33
valid_sources[0x16]	382233	1			T1	14		T2	26		T3	42
valid_sources[0x17]	303810	1			T1	20		T2	24		T3	49
valid_sources[0x18]	324717	1			T1	9		T2	20		T3	46
valid_sources[0x19]	393652	1			T1	8		T2	41		T3	42
valid_sources[0x1a]	334259	1			T1	10		T2	13		T3	34
valid_sources[0x1b]	322702	1			T1	6		T2	35		T3	47
valid_sources[0x1c]	334694	1			T1	17		T2	19		T3	57
valid_sources[0x1d]	361154	1			T1	24		T2	63		T3	58
valid_sources[0x1e]	320780	1			T1	2		T2	21		T3	38
valid_sources[0x1f]	319405	1			T1	13		T2	10		T3	38
valid_sources[0x20]	346676	1			T1	15		T2	25		T3	49
valid_sources[0x21]	347128	1			T1	4		T2	38		T3	37
valid_sources[0x22]	323617	1			T1	10		T2	25		T3	43
valid_sources[0x23]	338814	1			T1	24		T2	29		T3	43
valid_sources[0x24]	357330	1			T1	11		T2	36		T3	46
valid_sources[0x25]	329940	1			T1	2		T2	14		T3	45
valid_sources[0x26]	333227	1			T1	13		T2	36		T3	55
valid_sources[0x27]	397118	1			T1	5		T2	46		T3	49
valid_sources[0x28]	322410	1			T1	10		T2	6		T3	30
valid_sources[0x29]	355222	1			T1	15		T2	45		T3	37
valid_sources[0x2a]	351465	1			T1	28		T2	13		T3	33
valid_sources[0x2b]	397074	1			T1	22		T2	13		T3	48
valid_sources[0x2c]	316726	1			T1	4		T2	21		T3	47
valid_sources[0x2d]	333327	1			T1	5		T2	57		T3	43
valid_sources[0x2e]	337635	1			T1	8		T2	42		T3	47
valid_sources[0x2f]	405392	1			T1	10		T2	27		T3	40
valid_sources[0x30]	328295	1			T1	14		T2	22		T3	42
valid_sources[0x31]	342096	1			T1	26		T2	22		T3	45
valid_sources[0x32]	339566	1			T1	7		T2	28		T3	45
valid_sources[0x33]	346348	1			T1	9		T2	31		T3	51
valid_sources[0x34]	341994	1			T1	27		T2	40		T3	41
valid_sources[0x35]	348511	1			T1	27		T2	40		T3	42
valid_sources[0x36]	343923	1			T1	27		T2	25		T3	37
valid_sources[0x37]	333957	1			T1	10		T2	49		T3	52
valid_sources[0x38]	316604	1			T1	2		T2	15		T3	39
valid_sources[0x39]	340978	1			T1	6		T2	44		T3	48
valid_sources[0x3a]	320913	1			T1	28		T2	41		T3	35
valid_sources[0x3b]	342992	1			T1	10		T2	30		T3	37
valid_sources[0x3c]	346031	1			T1	12		T2	36		T3	52
valid_sources[0x3d]	473601	1			T1	18		T2	23		T3	37
valid_sources[0x3e]	363383	1			T1	6		T2	75		T3	51
valid_sources[0x3f]	355727	1			T1	7		T2	25		T3	43
valid_sources[0x40]	365338	1			T1	3		T2	24		T3	43
valid_sources[0x41]	331989	1			T1	11		T2	45		T3	51
valid_sources[0x42]	336406	1			T1	20		T2	66		T3	44
valid_sources[0x43]	330433	1			T1	11		T2	57		T3	40
valid_sources[0x44]	315405	1			T1	22		T2	46		T3	50
valid_sources[0x45]	388936	1			T1	2		T2	36		T3	39
valid_sources[0x46]	375359	1			T1	27		T2	24		T3	42
valid_sources[0x47]	539673	1			T1	13		T2	39		T3	40
valid_sources[0x48]	362899	1			T1	19		T2	53		T3	49
valid_sources[0x49]	363566	1			T1	1		T2	55		T3	27
valid_sources[0x4a]	336871	1			T1	38		T2	6		T3	33
valid_sources[0x4b]	375597	1			T1	11		T2	37		T3	58
valid_sources[0x4c]	321957	1			T1	32		T2	26		T3	55
valid_sources[0x4d]	334367	1			T1	12		T2	32		T3	35
valid_sources[0x4e]	324519	1			T1	8		T2	24		T3	47
valid_sources[0x4f]	333114	1			T1	20		T2	19		T3	45
valid_sources[0x50]	430403	1			T1	10		T2	20		T3	48
valid_sources[0x51]	400879	1			T1	28		T2	24		T3	42
valid_sources[0x52]	352707	1			T1	22		T2	24		T3	55
valid_sources[0x53]	374023	1			T1	14		T2	22		T3	37
valid_sources[0x54]	329972	1			T1	9		T2	39		T3	37
valid_sources[0x55]	341299	1			T1	3		T2	60		T3	48
valid_sources[0x56]	311318	1			T1	8		T2	18		T3	25
valid_sources[0x57]	325756	1			T1	16		T2	54		T3	46
valid_sources[0x58]	309034	1			T1	28		T2	9		T3	48
valid_sources[0x59]	357827	1			T1	16		T2	38		T3	46
valid_sources[0x5a]	346365	1			T1	31		T2	37		T3	66
valid_sources[0x5b]	316860	1			T1	36		T2	48		T3	42
valid_sources[0x5c]	360852	1			T1	9		T2	65		T3	41
valid_sources[0x5d]	336406	1			T1	22		T2	37		T3	50
valid_sources[0x5e]	340314	1			T1	17		T2	17		T3	51
valid_sources[0x5f]	339241	1			T1	13		T2	44		T3	40
valid_sources[0x60]	458478	1			T1	15		T2	55		T3	48
valid_sources[0x61]	339884	1			T1	10		T2	21		T3	32
valid_sources[0x62]	323294	1			T1	5		T2	6		T3	49
valid_sources[0x63]	320077	1			T1	9		T2	35		T3	56
valid_sources[0x64]	339906	1			T1	4		T2	53		T3	48
valid_sources[0x65]	334209	1			T1	29		T2	26		T3	34
valid_sources[0x66]	323071	1			T1	14		T2	43		T3	48
valid_sources[0x67]	327187	1			T1	6		T2	43		T3	42
valid_sources[0x68]	341916	1			T1	6		T2	50		T3	44
valid_sources[0x69]	313475	1			T1	17		T2	44		T3	45
valid_sources[0x6a]	355456	1			T1	19		T2	37		T3	49
valid_sources[0x6b]	345984	1			T1	7		T2	18		T3	29
valid_sources[0x6c]	341255	1			T1	4		T2	30		T3	48
valid_sources[0x6d]	318556	1			T1	14		T2	49		T3	47
valid_sources[0x6e]	318605	1			T1	16		T2	34		T3	47
valid_sources[0x6f]	323669	1			T1	24		T2	47		T3	36
valid_sources[0x70]	332906	1			T1	14		T2	27		T3	40
valid_sources[0x71]	352858	1			T1	18		T2	53		T3	41
valid_sources[0x72]	330675	1			T1	8		T2	26		T3	35
valid_sources[0x73]	319272	1			T1	13		T2	62		T3	50
valid_sources[0x74]	389084	1			T1	13		T2	25		T3	42
valid_sources[0x75]	340790	1			T1	13		T2	5		T3	41
valid_sources[0x76]	325694	1			T1	9		T2	27		T3	43
valid_sources[0x77]	311539	1			T1	13		T2	27		T3	55
valid_sources[0x78]	323722	1			T1	23		T2	66		T3	51
valid_sources[0x79]	370131	1			T1	21		T2	62		T3	44
valid_sources[0x7a]	308272	1			T1	4		T2	34		T3	48
valid_sources[0x7b]	337660	1			T1	15		T2	30		T3	53
valid_sources[0x7c]	357274	1			T1	13		T2	36		T3	43
valid_sources[0x7d]	312505	1			T1	8		T2	46		T3	33
valid_sources[0x7e]	333764	1			T1	16		T2	71		T3	49
valid_sources[0x7f]	339837	1			T1	16		T2	27		T3	59
valid_sources[0x80]	328385	1			T1	10		T2	54		T3	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17998221

1

T1

322

T2

45

T3

5

values[0x0]

all_enables

biggest_size

3332516

1

T1

84

T2

76

T3

3

values[0x1]

all_enables

biggest_size

3278862

1

T1

62

T2

47

T4

65340