Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
249684 |
520108 |
0 |
0 |
T2 |
201392 |
848084 |
0 |
0 |
T3 |
1090756 |
24214 |
0 |
0 |
T4 |
1193186 |
1217819 |
0 |
0 |
T5 |
813630 |
702885 |
0 |
0 |
T6 |
220162 |
529710 |
0 |
0 |
T7 |
258136 |
6864 |
0 |
0 |
T8 |
518790 |
563729 |
0 |
0 |
T9 |
114122 |
1394 |
0 |
0 |
T10 |
264498 |
175726 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
249684 |
249682 |
0 |
0 |
T2 |
201392 |
201372 |
0 |
0 |
T3 |
1090756 |
1090638 |
0 |
0 |
T4 |
1193186 |
1193170 |
0 |
0 |
T5 |
813630 |
813618 |
0 |
0 |
T6 |
220162 |
220160 |
0 |
0 |
T7 |
258136 |
257964 |
0 |
0 |
T8 |
518790 |
518776 |
0 |
0 |
T9 |
114122 |
114014 |
0 |
0 |
T10 |
264498 |
264486 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
249684 |
249682 |
0 |
0 |
T2 |
201392 |
201372 |
0 |
0 |
T3 |
1090756 |
1090638 |
0 |
0 |
T4 |
1193186 |
1193170 |
0 |
0 |
T5 |
813630 |
813618 |
0 |
0 |
T6 |
220162 |
220160 |
0 |
0 |
T7 |
258136 |
257964 |
0 |
0 |
T8 |
518790 |
518776 |
0 |
0 |
T9 |
114122 |
114014 |
0 |
0 |
T10 |
264498 |
264486 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
249684 |
249682 |
0 |
0 |
T2 |
201392 |
201372 |
0 |
0 |
T3 |
1090756 |
1090638 |
0 |
0 |
T4 |
1193186 |
1193170 |
0 |
0 |
T5 |
813630 |
813618 |
0 |
0 |
T6 |
220162 |
220160 |
0 |
0 |
T7 |
258136 |
257964 |
0 |
0 |
T8 |
518790 |
518776 |
0 |
0 |
T9 |
114122 |
114014 |
0 |
0 |
T10 |
264498 |
264486 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
249684 |
520108 |
0 |
0 |
T2 |
201392 |
848084 |
0 |
0 |
T3 |
1090756 |
24214 |
0 |
0 |
T4 |
1193186 |
1217819 |
0 |
0 |
T5 |
813630 |
702885 |
0 |
0 |
T6 |
220162 |
529710 |
0 |
0 |
T7 |
258136 |
6864 |
0 |
0 |
T8 |
518790 |
563729 |
0 |
0 |
T9 |
114122 |
1394 |
0 |
0 |
T10 |
264498 |
175726 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1711983964 |
0 |
0 |
T1 |
124842 |
117956 |
0 |
0 |
T2 |
100696 |
457683 |
0 |
0 |
T3 |
545378 |
10 |
0 |
0 |
T4 |
596593 |
860261 |
0 |
0 |
T5 |
406815 |
297460 |
0 |
0 |
T6 |
110081 |
108253 |
0 |
0 |
T7 |
129068 |
10 |
0 |
0 |
T8 |
259395 |
559781 |
0 |
0 |
T9 |
57061 |
10 |
0 |
0 |
T10 |
132249 |
165430 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
124842 |
124841 |
0 |
0 |
T2 |
100696 |
100686 |
0 |
0 |
T3 |
545378 |
545319 |
0 |
0 |
T4 |
596593 |
596585 |
0 |
0 |
T5 |
406815 |
406809 |
0 |
0 |
T6 |
110081 |
110080 |
0 |
0 |
T7 |
129068 |
128982 |
0 |
0 |
T8 |
259395 |
259388 |
0 |
0 |
T9 |
57061 |
57007 |
0 |
0 |
T10 |
132249 |
132243 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
124842 |
124841 |
0 |
0 |
T2 |
100696 |
100686 |
0 |
0 |
T3 |
545378 |
545319 |
0 |
0 |
T4 |
596593 |
596585 |
0 |
0 |
T5 |
406815 |
406809 |
0 |
0 |
T6 |
110081 |
110080 |
0 |
0 |
T7 |
129068 |
128982 |
0 |
0 |
T8 |
259395 |
259388 |
0 |
0 |
T9 |
57061 |
57007 |
0 |
0 |
T10 |
132249 |
132243 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
124842 |
124841 |
0 |
0 |
T2 |
100696 |
100686 |
0 |
0 |
T3 |
545378 |
545319 |
0 |
0 |
T4 |
596593 |
596585 |
0 |
0 |
T5 |
406815 |
406809 |
0 |
0 |
T6 |
110081 |
110080 |
0 |
0 |
T7 |
129068 |
128982 |
0 |
0 |
T8 |
259395 |
259388 |
0 |
0 |
T9 |
57061 |
57007 |
0 |
0 |
T10 |
132249 |
132243 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1711983964 |
0 |
0 |
T1 |
124842 |
117956 |
0 |
0 |
T2 |
100696 |
457683 |
0 |
0 |
T3 |
545378 |
10 |
0 |
0 |
T4 |
596593 |
860261 |
0 |
0 |
T5 |
406815 |
297460 |
0 |
0 |
T6 |
110081 |
108253 |
0 |
0 |
T7 |
129068 |
10 |
0 |
0 |
T8 |
259395 |
559781 |
0 |
0 |
T9 |
57061 |
10 |
0 |
0 |
T10 |
132249 |
165430 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T11,T12 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T11,T12 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
631812394 |
0 |
0 |
T1 |
124842 |
402152 |
0 |
0 |
T2 |
100696 |
390401 |
0 |
0 |
T3 |
545378 |
24204 |
0 |
0 |
T4 |
596593 |
357558 |
0 |
0 |
T5 |
406815 |
405425 |
0 |
0 |
T6 |
110081 |
421457 |
0 |
0 |
T7 |
129068 |
6854 |
0 |
0 |
T8 |
259395 |
3948 |
0 |
0 |
T9 |
57061 |
1384 |
0 |
0 |
T10 |
132249 |
10296 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
124842 |
124841 |
0 |
0 |
T2 |
100696 |
100686 |
0 |
0 |
T3 |
545378 |
545319 |
0 |
0 |
T4 |
596593 |
596585 |
0 |
0 |
T5 |
406815 |
406809 |
0 |
0 |
T6 |
110081 |
110080 |
0 |
0 |
T7 |
129068 |
128982 |
0 |
0 |
T8 |
259395 |
259388 |
0 |
0 |
T9 |
57061 |
57007 |
0 |
0 |
T10 |
132249 |
132243 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
124842 |
124841 |
0 |
0 |
T2 |
100696 |
100686 |
0 |
0 |
T3 |
545378 |
545319 |
0 |
0 |
T4 |
596593 |
596585 |
0 |
0 |
T5 |
406815 |
406809 |
0 |
0 |
T6 |
110081 |
110080 |
0 |
0 |
T7 |
129068 |
128982 |
0 |
0 |
T8 |
259395 |
259388 |
0 |
0 |
T9 |
57061 |
57007 |
0 |
0 |
T10 |
132249 |
132243 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
124842 |
124841 |
0 |
0 |
T2 |
100696 |
100686 |
0 |
0 |
T3 |
545378 |
545319 |
0 |
0 |
T4 |
596593 |
596585 |
0 |
0 |
T5 |
406815 |
406809 |
0 |
0 |
T6 |
110081 |
110080 |
0 |
0 |
T7 |
129068 |
128982 |
0 |
0 |
T8 |
259395 |
259388 |
0 |
0 |
T9 |
57061 |
57007 |
0 |
0 |
T10 |
132249 |
132243 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
631812394 |
0 |
0 |
T1 |
124842 |
402152 |
0 |
0 |
T2 |
100696 |
390401 |
0 |
0 |
T3 |
545378 |
24204 |
0 |
0 |
T4 |
596593 |
357558 |
0 |
0 |
T5 |
406815 |
405425 |
0 |
0 |
T6 |
110081 |
421457 |
0 |
0 |
T7 |
129068 |
6854 |
0 |
0 |
T8 |
259395 |
3948 |
0 |
0 |
T9 |
57061 |
1384 |
0 |
0 |
T10 |
132249 |
10296 |
0 |
0 |