Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	10837391	0	0
ctrl_rd_A	2147483647	187653	0	0
intr_enable_rd_A	2147483647	167891	0	0
ovrd_rd_A	2147483647	188194	0	0
timeout_ctrl_rd_A	2147483647	189497	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10837391	0	0
T4	596593	232515	0	0
T5	406815	0	0	0
T6	110081	0	0	0
T7	129068	0	0	0
T8	259395	0	0	0
T9	57061	0	0	0
T10	132249	0	0	0
T14	0	215766	0	0
T16	401763	153648	0	0
T29	0	85859	0	0
T30	0	161430	0	0
T31	0	71853	0	0
T32	0	68322	0	0
T33	0	70696	0	0
T34	0	43100	0	0
T35	0	68964	0	0
T36	509241	0	0	0
T37	189022	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	187653	0	0
T31	405164	7705	0	0
T34	0	4896	0	0
T99	0	4120	0	0
T100	0	9565	0	0
T101	0	10919	0	0
T102	0	10880	0	0
T103	0	5662	0	0
T104	0	5161	0	0
T105	0	6575	0	0
T106	0	2194	0	0
T107	631454	0	0	0
T108	1470	0	0	0
T109	88626	0	0	0
T110	373430	0	0	0
T111	474975	0	0	0
T112	45192	0	0	0
T113	1336	0	0	0
T114	668852	0	0	0
T115	114060	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	167891	0	0
T31	405164	7377	0	0
T34	0	4353	0	0
T99	0	3329	0	0
T100	0	8553	0	0
T101	0	9233	0	0
T102	0	9449	0	0
T103	0	4790	0	0
T104	0	4591	0	0
T107	631454	0	0	0
T108	1470	0	0	0
T109	88626	0	0	0
T110	373430	0	0	0
T111	474975	0	0	0
T112	45192	0	0	0
T113	1336	0	0	0
T114	668852	0	0	0
T115	114060	0	0	0
T116	0	7	0	0
T117	0	14	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	188194	0	0
T31	405164	8207	0	0
T34	0	4636	0	0
T99	0	3490	0	0
T100	0	9311	0	0
T101	0	10938	0	0
T102	0	10789	0	0
T103	0	6043	0	0
T104	0	5420	0	0
T105	0	6553	0	0
T106	0	2367	0	0
T107	631454	0	0	0
T108	1470	0	0	0
T109	88626	0	0	0
T110	373430	0	0	0
T111	474975	0	0	0
T112	45192	0	0	0
T113	1336	0	0	0
T114	668852	0	0	0
T115	114060	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	189497	0	0
T31	405164	8843	0	0
T34	0	4835	0	0
T99	0	3703	0	0
T100	0	9795	0	0
T101	0	11183	0	0
T102	0	11035	0	0
T103	0	5576	0	0
T104	0	5363	0	0
T105	0	6630	0	0
T106	0	2169	0	0
T107	631454	0	0	0
T108	1470	0	0	0
T109	88626	0	0	0
T110	373430	0	0	0
T111	474975	0	0	0
T112	45192	0	0	0
T113	1336	0	0	0
T114	668852	0	0	0
T115	114060	0	0	0