Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66914721	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21755598

1

T1

18

T2

121

T3

367

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82786496	1			T1	10615		T2	7070		T3	735
values[0x0]	2789020	1			T1	21		T2	81		T3	156
values[0x1]	3094803	1			T1	29		T2	66		T3	130

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46344561	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42325758

1

T1

3574

T2

2513

T3

511

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	350319	1			T1	35		T2	26		T3	3
valid_sources[0x01]	398927	1			T1	34		T3	2		T4	52
valid_sources[0x02]	381471	1			T1	37		T2	9		T3	4
valid_sources[0x03]	341084	1			T1	31		T2	54		T3	3
valid_sources[0x04]	370717	1			T1	46		T2	60		T3	4
valid_sources[0x05]	365611	1			T1	37		T2	3		T3	4
valid_sources[0x06]	324652	1			T1	29		T2	54		T4	30
valid_sources[0x07]	415454	1			T1	39		T2	8		T3	4
valid_sources[0x08]	374492	1			T1	41		T2	9		T3	7
valid_sources[0x09]	339301	1			T1	36		T2	29		T4	37
valid_sources[0x0a]	334968	1			T1	28		T2	10		T3	10
valid_sources[0x0b]	314922	1			T1	36		T2	29		T4	31
valid_sources[0x0c]	429187	1			T1	56		T2	36		T4	27
valid_sources[0x0d]	360004	1			T1	39		T2	56		T3	2
valid_sources[0x0e]	327436	1			T1	44		T2	37		T3	4
valid_sources[0x0f]	346712	1			T1	54		T2	48		T3	2
valid_sources[0x10]	331767	1			T1	42		T2	47		T4	37
valid_sources[0x11]	349066	1			T1	45		T2	2		T3	5
valid_sources[0x12]	319887	1			T1	44		T2	20		T3	7
valid_sources[0x13]	356588	1			T1	46		T2	12		T3	1
valid_sources[0x14]	336994	1			T1	49		T2	59		T3	7
valid_sources[0x15]	329255	1			T1	33		T2	6		T3	4
valid_sources[0x16]	313906	1			T1	51		T2	4		T4	18
valid_sources[0x17]	343990	1			T1	33		T2	21		T4	27
valid_sources[0x18]	313415	1			T1	36		T2	9		T3	1
valid_sources[0x19]	344812	1			T1	31		T2	56		T3	3
valid_sources[0x1a]	358619	1			T1	51		T2	19		T3	1
valid_sources[0x1b]	319964	1			T1	46		T2	52		T3	8
valid_sources[0x1c]	319149	1			T1	36		T2	12		T4	19
valid_sources[0x1d]	332123	1			T1	58		T2	18		T3	4
valid_sources[0x1e]	331689	1			T1	45		T2	32		T3	2
valid_sources[0x1f]	345114	1			T1	42		T2	30		T3	8
valid_sources[0x20]	396972	1			T1	35		T2	43		T4	36
valid_sources[0x21]	348839	1			T1	47		T2	22		T3	4
valid_sources[0x22]	366770	1			T1	35		T2	17		T3	4
valid_sources[0x23]	366114	1			T1	40		T2	24		T3	4
valid_sources[0x24]	322245	1			T1	35		T2	7		T3	13
valid_sources[0x25]	333369	1			T1	44		T2	35		T3	4
valid_sources[0x26]	304720	1			T1	31		T2	62		T3	7
valid_sources[0x27]	407045	1			T1	39		T2	10		T3	5
valid_sources[0x28]	352589	1			T1	42		T2	32		T4	46
valid_sources[0x29]	327691	1			T1	48		T2	13		T3	1
valid_sources[0x2a]	313482	1			T1	32		T2	15		T4	12
valid_sources[0x2b]	497221	1			T1	31		T2	34		T3	2
valid_sources[0x2c]	329065	1			T1	46		T2	62		T3	5
valid_sources[0x2d]	325665	1			T1	43		T2	5		T3	2
valid_sources[0x2e]	344942	1			T1	29		T2	22		T4	10
valid_sources[0x2f]	371449	1			T1	45		T2	32		T3	5
valid_sources[0x30]	314576	1			T1	43		T2	42		T3	6
valid_sources[0x31]	339683	1			T1	37		T2	43		T3	5
valid_sources[0x32]	325458	1			T1	53		T2	34		T3	1
valid_sources[0x33]	321514	1			T1	49		T2	46		T3	2
valid_sources[0x34]	325488	1			T1	29		T2	18		T3	6
valid_sources[0x35]	326110	1			T1	47		T2	3		T3	17
valid_sources[0x36]	336012	1			T1	38		T2	21		T3	4
valid_sources[0x37]	344246	1			T1	43		T2	37		T3	1
valid_sources[0x38]	348368	1			T1	42		T2	39		T4	24
valid_sources[0x39]	332096	1			T1	45		T2	81		T3	12
valid_sources[0x3a]	358300	1			T1	49		T2	29		T3	6
valid_sources[0x3b]	322888	1			T1	51		T2	15		T3	2
valid_sources[0x3c]	318715	1			T1	56		T2	39		T3	6
valid_sources[0x3d]	327630	1			T1	29		T2	59		T3	10
valid_sources[0x3e]	361667	1			T1	29		T2	27		T3	2
valid_sources[0x3f]	371127	1			T1	45		T2	44		T3	9
valid_sources[0x40]	367856	1			T1	51		T2	24		T3	4
valid_sources[0x41]	321328	1			T1	40		T2	32		T3	2
valid_sources[0x42]	318825	1			T1	31		T2	20		T3	1
valid_sources[0x43]	339766	1			T1	50		T2	62		T3	2
valid_sources[0x44]	337227	1			T1	44		T2	39		T3	6
valid_sources[0x45]	330211	1			T1	40		T2	46		T3	2
valid_sources[0x46]	329522	1			T1	50		T2	43		T3	4
valid_sources[0x47]	329596	1			T1	33		T2	22		T4	17
valid_sources[0x48]	344529	1			T1	35		T2	27		T4	40
valid_sources[0x49]	360265	1			T1	45		T2	57		T3	2
valid_sources[0x4a]	317229	1			T1	36		T2	53		T3	3
valid_sources[0x4b]	337299	1			T1	34		T2	81		T3	8
valid_sources[0x4c]	346627	1			T1	53		T2	4		T3	2
valid_sources[0x4d]	317094	1			T1	42		T2	68		T3	1
valid_sources[0x4e]	350915	1			T1	28		T3	4		T4	52
valid_sources[0x4f]	320709	1			T1	46		T2	26		T3	1
valid_sources[0x50]	435091	1			T1	34		T2	10		T3	11
valid_sources[0x51]	318410	1			T1	50		T2	46		T4	39
valid_sources[0x52]	343861	1			T1	33		T2	43		T3	5
valid_sources[0x53]	378029	1			T1	46		T2	72		T3	7
valid_sources[0x54]	348618	1			T1	38		T2	29		T3	23
valid_sources[0x55]	393515	1			T1	43		T2	26		T3	6
valid_sources[0x56]	330200	1			T1	34		T2	26		T3	4
valid_sources[0x57]	341017	1			T1	48		T2	31		T3	10
valid_sources[0x58]	344634	1			T1	40		T2	64		T3	4
valid_sources[0x59]	384907	1			T1	23		T2	48		T3	6
valid_sources[0x5a]	335740	1			T1	34		T2	35		T3	3
valid_sources[0x5b]	355383	1			T1	44		T2	14		T3	3
valid_sources[0x5c]	356307	1			T1	32		T2	14		T3	9
valid_sources[0x5d]	350212	1			T1	48		T2	44		T3	1
valid_sources[0x5e]	315799	1			T1	44		T2	24		T3	8
valid_sources[0x5f]	365064	1			T1	32		T2	20		T3	6
valid_sources[0x60]	369583	1			T1	59		T2	21		T3	7
valid_sources[0x61]	302666	1			T1	37		T2	39		T3	15
valid_sources[0x62]	339386	1			T1	36		T2	22		T3	10
valid_sources[0x63]	338558	1			T1	44		T2	55		T3	7
valid_sources[0x64]	364810	1			T1	46		T2	44		T4	30
valid_sources[0x65]	335953	1			T1	50		T2	20		T3	1
valid_sources[0x66]	419501	1			T1	40		T2	12		T3	6
valid_sources[0x67]	432401	1			T1	42		T2	45		T3	6
valid_sources[0x68]	539994	1			T1	31		T2	27		T3	5
valid_sources[0x69]	350806	1			T1	52		T2	38		T3	6
valid_sources[0x6a]	323755	1			T1	49		T2	12		T3	4
valid_sources[0x6b]	328995	1			T1	31		T2	42		T3	3
valid_sources[0x6c]	380439	1			T1	40		T2	9		T3	4
valid_sources[0x6d]	353107	1			T1	35		T2	21		T3	10
valid_sources[0x6e]	333499	1			T1	72		T2	37		T4	33
valid_sources[0x6f]	333361	1			T1	44		T2	8		T3	3
valid_sources[0x70]	339800	1			T1	49		T2	64		T3	8
valid_sources[0x71]	380905	1			T1	39		T2	12		T4	6
valid_sources[0x72]	420610	1			T1	34		T2	40		T3	4
valid_sources[0x73]	341147	1			T1	35		T2	17		T3	2
valid_sources[0x74]	326157	1			T1	57		T2	24		T3	2
valid_sources[0x75]	348517	1			T1	46		T2	62		T3	3
valid_sources[0x76]	315748	1			T1	43		T2	20		T4	19
valid_sources[0x77]	387094	1			T1	37		T2	14		T3	2
valid_sources[0x78]	320869	1			T1	48		T2	31		T3	4
valid_sources[0x79]	322271	1			T1	49		T2	13		T3	2
valid_sources[0x7a]	343796	1			T1	40		T2	6		T3	3
valid_sources[0x7b]	316205	1			T1	53		T2	28		T3	4
valid_sources[0x7c]	420364	1			T1	38		T2	13		T3	1
valid_sources[0x7d]	351703	1			T1	41		T2	1		T3	5
valid_sources[0x7e]	323329	1			T1	44		T2	38		T3	3
valid_sources[0x7f]	419944	1			T1	46		T2	16		T4	21
valid_sources[0x80]	329884	1			T1	37		T2	47		T4	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16670470

1

T1

3

T2

8

T3

277

values[0x0]

all_enables

biggest_size

2570485

1

T1

7

T2

62

T3

62

values[0x1]

all_enables

biggest_size

2514643

1

T1

8

T2

51

T3

28