Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	8262828	0	0
ctrl_rd_A	2147483647	150261	0	0
intr_enable_rd_A	2147483647	134338	0	0
ovrd_rd_A	2147483647	147951	0	0
timeout_ctrl_rd_A	2147483647	149003	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8262828	0	0
T8	235018	76992	0	0
T9	145906	0	0	0
T10	178588	0	0	0
T11	11016	0	0	0
T15	0	82699	0	0
T20	0	89992	0	0
T28	710608	0	0	0
T29	254764	0	0	0
T30	172028	0	0	0
T31	0	39680	0	0
T32	0	99669	0	0
T33	0	4956	0	0
T34	0	120956	0	0
T35	0	69475	0	0
T36	0	190354	0	0
T37	0	85359	0	0
T38	309479	0	0	0
T39	925349	0	0	0
T40	127014	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	150261	0	0
T19	121297	0	0	0
T33	170472	516	0	0
T34	0	3366	0	0
T35	0	8259	0	0
T36	0	20877	0	0
T37	0	2301	0	0
T42	214919	0	0	0
T43	305830	0	0	0
T52	0	6491	0	0
T92	0	12302	0	0
T93	0	5228	0	0
T94	0	10857	0	0
T95	0	3816	0	0
T96	110372	0	0	0
T97	813716	0	0	0
T98	153795	0	0	0
T99	246012	0	0	0
T100	162500	0	0	0
T101	143825	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	134338	0	0
T19	121297	0	0	0
T33	170472	406	0	0
T34	0	2717	0	0
T35	0	7430	0	0
T36	0	19389	0	0
T37	0	2006	0	0
T42	214919	0	0	0
T43	305830	0	0	0
T52	0	5586	0	0
T92	0	10880	0	0
T93	0	4599	0	0
T94	0	9473	0	0
T96	110372	0	0	0
T97	813716	0	0	0
T98	153795	0	0	0
T99	246012	0	0	0
T100	162500	0	0	0
T101	143825	0	0	0
T102	0	24	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	147951	0	0
T19	121297	0	0	0
T33	170472	547	0	0
T34	0	3126	0	0
T35	0	8327	0	0
T36	0	21577	0	0
T37	0	2271	0	0
T42	214919	0	0	0
T43	305830	0	0	0
T52	0	6419	0	0
T92	0	13164	0	0
T93	0	5039	0	0
T94	0	10608	0	0
T95	0	3857	0	0
T96	110372	0	0	0
T97	813716	0	0	0
T98	153795	0	0	0
T99	246012	0	0	0
T100	162500	0	0	0
T101	143825	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	149003	0	0
T19	121297	0	0	0
T33	170472	504	0	0
T34	0	3064	0	0
T35	0	8110	0	0
T36	0	21494	0	0
T37	0	2371	0	0
T42	214919	0	0	0
T43	305830	0	0	0
T52	0	6433	0	0
T92	0	12411	0	0
T93	0	5274	0	0
T94	0	10189	0	0
T95	0	4172	0	0
T96	110372	0	0	0
T97	813716	0	0	0
T98	153795	0	0	0
T99	246012	0	0	0
T100	162500	0	0	0
T101	143825	0	0	0