UART Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	59.330s	11.111ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	35.668us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	34.179us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.490s	1.873ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.830s	32.118us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.410s	31.937us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	34.179us	20	20	100.00
		uart_csr_aliasing	0.830s	32.118us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.610m	127.014ms	50	50	100.00
V2	parity	uart_smoke	59.330s	11.111ms	50	50	100.00
		uart_tx_rx	4.610m	127.014ms	50	50	100.00
V2	parity_error	uart_intr	6.684m	414.565ms	50	50	100.00
		uart_rx_parity_err	3.593m	134.461ms	50	50	100.00
V2	watermark	uart_tx_rx	4.610m	127.014ms	50	50	100.00
		uart_intr	6.684m	414.565ms	50	50	100.00
V2	fifo_full	uart_fifo_full	9.911m	258.790ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.020m	64.412ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.314m	133.576ms	299	300	99.67
V2	rx_frame_err	uart_intr	6.684m	414.565ms	50	50	100.00
V2	rx_break_err	uart_intr	6.684m	414.565ms	50	50	100.00
V2	rx_timeout	uart_intr	6.684m	414.565ms	50	50	100.00
V2	perf	uart_perf	26.077m	30.942ms	50	50	100.00
V2	sys_loopback	uart_loopback	25.040s	13.833ms	50	50	100.00
V2	line_loopback	uart_loopback	25.040s	13.833ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.083m	52.669ms	8	50	16.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.176m	43.843ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	40.010s	6.916ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.080m	6.533ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.682m	126.149ms	50	50	100.00
V2	stress_all	uart_stress_all	23.207m	67.212ms	34	50	68.00
V2	alert_test	uart_alert_test	0.620s	33.891us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	14.253us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.720s	261.529us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.720s	261.529us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	35.668us	5	5	100.00
		uart_csr_rw	0.640s	34.179us	20	20	100.00
		uart_csr_aliasing	0.830s	32.118us	5	5	100.00
		uart_same_csr_outstanding	0.790s	468.455us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	35.668us	5	5	100.00
		uart_csr_rw	0.640s	34.179us	20	20	100.00
		uart_csr_aliasing	0.830s	32.118us	5	5	100.00
		uart_same_csr_outstanding	0.790s	468.455us	20	20	100.00
V2		TOTAL			1031	1090	94.59
V2S	tl_intg_err	uart_sec_cm	0.870s	72.595us	5	5	100.00
		uart_tl_intg_err	1.370s	250.352us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.370s	250.352us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	42.165m	92.862ms	61	100	61.00
V3		TOTAL			61	100	61.00
		TOTAL			1222	1320	92.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 47 failures:

  • Test uart_noise_filter has 20 failures.

    • 0.uart_noise_filter.27708359291415299082313250228235702403786093196386657140201971779071618706192
      Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @  80441741 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  80441741 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 1410282123 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1410282123 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 2639836553 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • 2.uart_noise_filter.35886590105387596528484047831685039187713003095925862242362967873789197967713
      Line 253, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_noise_filter/latest/run.log

        UVM_ERROR @ 33867626939 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 33867626939 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 33960796939 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 33975136939 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
        UVM_ERROR @ 33975156939 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
      

    • ... and 18 more failures.

  • Test uart_stress_all_with_rand_reset has 19 failures.

    • 5.uart_stress_all_with_rand_reset.65296394154860222196973750914680972532034449484330264546436528390511522046888
      Line 523, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 47783971148 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 47783971148 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_INFO @ 47814887320 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 234/766
        UVM_ERROR @ 47876948827 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 47877157157 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 15 [0xf]) reg name: uart_reg_block.rdata
      

    • 8.uart_stress_all_with_rand_reset.39012175151699632099820486764120637504909702239833653309838942622374365235488
      Line 999, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 91962670664 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 91963599228 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 91964527792 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 91965456356 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 91966384920 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 17 more failures.

  • Test uart_stress_all has 8 failures.

    • 8.uart_stress_all.89185847785655739382106589165774863270000142628143732257971170178726531579040
      Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_stress_all/latest/run.log

        UVM_ERROR @ 52935132382 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 53325333342 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 53328047606 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 53471250542 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 53605555590 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • 11.uart_stress_all.35980228765651031232735464693366224792043562699480544607541659503917763667072
      Line 268, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_stress_all/latest/run.log

        UVM_ERROR @ 68594777023 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 68600832627 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 68609846588 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 68612166051 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 68618818882 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 6 more failures.

• UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 23 failures:

  • Test uart_stress_all_with_rand_reset has 10 failures.

    • 0.uart_stress_all_with_rand_reset.86045569786597299563048081184947455597700146922144713084930494869521748311664
      Line 417, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35294684415 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 35294684415 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 35305004415 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 35305004415 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 35312364415 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
      

    • 7.uart_stress_all_with_rand_reset.9643613305533901005924223349809778649737068006768992576986850420347735744533
      Line 453, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 618367526674 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 618367526674 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 618367526674 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 618413276674 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 619059526674 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 6,                                 clk_pulses: 6
      

    • ... and 8 more failures.

  • Test uart_noise_filter has 9 failures.

    • 6.uart_noise_filter.63494958243918837330013557654969146079698616466545975495028064810116702127531
      Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_noise_filter/latest/run.log

        UVM_ERROR @ 35204828220 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 35204828220 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 35204828220 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 35219953220 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 35273578220 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5,                                 clk_pulses: 0
      

    • 7.uart_noise_filter.68285745898824110417958310125586732882140540289482023551230616670991197598550
      Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_noise_filter/latest/run.log

        UVM_ERROR @ 308939799 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 308939799 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 313733484 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 314001518 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 314001518 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 7 more failures.

  • Test uart_stress_all has 4 failures.

    • 21.uart_stress_all.55813988782966999307493289024713014963600536370923818274258303217508310235486
      Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_stress_all/latest/run.log

        UVM_ERROR @ 80684293449 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 80684293449 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 80684293449 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 81281369775 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 81281523621 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (73 [0x49] vs 239 [0xef]) reg name: uart_reg_block.rdata
      

    • 31.uart_stress_all.42896185718319909909320530189343851549755090247465098461072987081097673881227
      Line 316, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_stress_all/latest/run.log

        UVM_ERROR @ 134505503916 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 134505503916 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 134505503916 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 134555045843 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 134637367136 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 4,                                 clk_pulses: 0
      

    • ... and 2 more failures.

• UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 19 failures:

  • Test uart_noise_filter has 12 failures.

    • 1.uart_noise_filter.87169830453849892812141768401572700642409527125812159541401973272783650481483
      Line 253, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_noise_filter/latest/run.log

        UVM_ERROR @ 24126439589 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 24126449690 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 24126500195 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (50 [0x32] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 24126510296 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 24126550700 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (50 [0x32] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

    • 4.uart_noise_filter.1092252616382020430542594813256434369056789293311307986613552030240521179281
      Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_noise_filter/latest/run.log

        UVM_ERROR @ 70731737442 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 70731862442 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 70731987442 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (188 [0xbc] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 71829237442 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 71829237442 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 10 more failures.

  • Test uart_stress_all has 1 failures.

    • 2.uart_stress_all.14089906726068997834777991810663145161835605086703365020860928988174012770664
      Line 261, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all/latest/run.log

        UVM_ERROR @ 44123323075 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 44123333713 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 44123344351 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 44239926193 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 44239926193 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

  • Test uart_stress_all_with_rand_reset has 6 failures.

    • 23.uart_stress_all_with_rand_reset.11680749882136066199170444426068344925304237500098944988010342547330408326356
      Line 401, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17163322450 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 17163342450 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 17163362450 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (91 [0x5b] vs 191 [0xbf]) reg name: uart_reg_block.rdata
        UVM_INFO @ 17251562450 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 80/500
        UVM_ERROR @ 17330162450 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • 40.uart_stress_all_with_rand_reset.96720564067320440269333738834785007575813694193403637822895191879999411919276
      Line 316, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9766633234 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 9766662646 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 9766692058 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_INFO @ 9822427798 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 10/401
        UVM_INFO @ 9982340842 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 11/401
      

    • ... and 4 more failures.

• UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

  • Test uart_stress_all has 2 failures.

    • 7.uart_stress_all.67026565916106873227428509973378833877447966826220316972521800801883605050417
      Line 295, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all/latest/run.log

        UVM_ERROR @ 34417459167 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
        UVM_INFO @ 34716631285 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/9
        UVM_INFO @ 35197205809 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/9
        UVM_INFO @ 36995574133 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/9
        UVM_INFO @ 37964437885 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/9
      

    • 23.uart_stress_all.70222168955720936194095520823730167310007856903518722983823237276653624960939
      Line 255, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_stress_all/latest/run.log

        UVM_ERROR @ 105506639276 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
        UVM_INFO @ 112164460030 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/7
        UVM_INFO @ 118274031318 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/7
        UVM_INFO @ 143314757076 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/7
        UVM_INFO @ 177077742770 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/7
      

  • Test uart_fifo_reset has 1 failures.

    • 150.uart_fifo_reset.1703928337385615320606134667179491227599179592265114604644930059081652903163
      Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/150.uart_fifo_reset/latest/run.log

        UVM_ERROR @   1431385 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
        UVM_INFO @ 7417231153 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/9
        UVM_INFO @ 10275205532 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/9
        UVM_INFO @ 13968889305 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/9
        UVM_INFO @ 13970188239 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/9
      

• UVM_ERROR (uart_intr_vseq.sv:312) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 3 failures:

  • Test uart_stress_all_with_rand_reset has 3 failures.

    • 64.uart_stress_all_with_rand_reset.37726203588613896349609738956938167406502048696818796029856330583277190539344
      Line 361, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 134625204190 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 135566604190 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
        Testing RxFrameErr
        UVM_INFO @ 135667604190 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
        Testing RxTimeout
      

    • 76.uart_stress_all_with_rand_reset.82439325170842987567094508816355854797302919368957565757815785893841749165366
      Line 305, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 55807532209 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
        UVM_ERROR @ 55807532209 ps: (uart_intr_vseq.sv:314) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 17e
        UVM_ERROR @ 56124532843 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
        UVM_ERROR @ 56124532843 ps: (uart_intr_vseq.sv:314) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 17e
        UVM_ERROR @ 56469366866 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
      

    • ... and 1 more failures.

• UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr has 2 failures:

  • Test uart_stress_all has 1 failures.

    • 27.uart_stress_all.55384992281795053633123685271367202062391427439524166418385701929323140243271
      Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/27.uart_stress_all/latest/run.log

        UVM_ERROR @ 2302940407 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 2302940407 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
        UVM_ERROR @ 2302940407 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
        UVM_ERROR @ 2306340407 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
        UVM_ERROR @ 2306340407 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
      

  • Test uart_noise_filter has 1 failures.

    • 28.uart_noise_filter.20731473542303917870536554068875804828815510066478310024192622446279793003518
      Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/28.uart_noise_filter/latest/run.log

        UVM_ERROR @ 1083758276 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 1083758276 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
        UVM_ERROR @ 1084398276 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 1084398276 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
        UVM_ERROR @ 1084608276 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
      

• UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 75.uart_stress_all_with_rand_reset.6340693717538752425995742330270225095195833434277668989141482473737171478932
      Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 369211085 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_INFO @ 384893609 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/401
        UVM_INFO @ 513496655 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/401
        UVM_INFO @ 560115656 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/401
        UVM_INFO @ 674623478 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/401
      

Past Results

• Latest
• lint
• 2024.06.25_11.47.45
• 2024.06.24_08.46.16
• 2024.06.23_08.09.18
• 2024.06.22_11.48.54
• 2024.06.14_07.33.17
• 2024.06.12_05.08.37